Hewlett-packard Development Company, L.P.

Hewlett Packard Enterprise Development LP

Nutanix, Inc.

Vanish Talwar

Parthasarathy Ranganathan

Sujoy Basu

Dejan S Milojicic

Rajendra Kumar

Yuan Chen

Zhikui Wang

Indrajit Roy

Chengwei Wang

Sanjay Kumar

Jeffrey R Hilland

Daniel Juergen Gmach

Partha Ranganathan

Dongni Chen

Xiaoyun Zhu

Choudur K Lakshminarayan

Krishnamurthy Viswanathan

Subramoniam N Iyer

Raj Kumar

Michael Mihn-Jong Lee

V Prashanth

Norman Paul Jouppi

Paolo Faraboschi

Zhichen Xu

Mustafa Uysal

Dwight L Barron

Alan Lynn Davis

Alvin AuYoung

Matteo Monchiero

Praveen Yalagandula

Luis E Luciani, Jr

Niraj Tolia

Clifford A McCarthy

Jeffrey S Autor

Wade James Satterfield

Gokul Nadathur

Troy Don Miller

Al Davis

Timothy F Forell

Jacob B Leverich

Sudarsun Kannan

Ramya Raghavendra

Tom Turicchi

Ks Sandeep

Vidhya Kannan

Sandeep Ks

Adit Madan

Prashanth V

Naila Farooqui

Vishakha Gupta

Adhikary Susanta

Shivakumar Bhavna

Sangman Kim

Misra Bharat

Parthasarthy Ranganathan

Jeff S Autor

Steve Ko

Bikash Agarwalla

Jeff Hilland

Susanta Adhikary

Chetan Shankar

Kannan Vidhya

In one example, a memory network may control access to a shared memory that is by multiple compute nodes. The memory network may control the access to the shared memory by receiving a memory access request originating from an application executing on the multiple compute nodes and determining a priority for processing the memory access request. The priority determined by the memory network may correspond to a memory address range in the memory that is specifically used by the application.

Memory network to prioritize processing of a memory access request

A system management command is stored in a management partition of a global memory by a first node of a multi-node computing system. The global memory is shared by each node of the multi-node computing system. In response to an indication to access the management partition, the system management command is accessed from the management partition by a second node of the multi-node computing system. The system management command is executed by the second node. Executing the system management command includes managing the second node.

Computing system management using shared memory

According to an example, an instruction to run a kernel of an application on an apparatus having a first processing unit integrated with a second processing unit may be received. In addition, an application profile for the application at a runtime of the application kernel on the second processing unit may be created, in which the application profile identifies an affinity of the application kernel to be run on either the first processing unit or the second processing unit, and identifies a characterization of an input data set of the application. The application profile may also be stored in a data store.

Integrated heterogeneous processing units

A system comprises a plurality of functional units powered via a power source. The system further comprises a first functional unit and a second functional unit, wherein the second functional unit is to promote the first functional unit to a management unit based on a management requirement of the system. The management unit is to administrate operations of the system. Once the first functional unit is promoted, the management unit is isolated from the functional units that were not promoted via a virtual network path and a power management unit.

Functional unit promotion to management unit

The communication between integrated graphics processing units (GPUs) is disclosed. A first integrated GPU of a first computing device obtains a tuple pertaining to data to be transmitted to a second integrated GPU of a second computing device. The tuple comprises at least a length of the data. The first integrated GPU allocates a virtual address space to the data based on the length of the data, where the virtual address space has a plurality of virtual addresses. Further, a mapping table of a mapping between the plurality of virtual addresses and a plurality of bus addresses is provided by the first integrated GPU to a communication module of the first computing device to transmit the data, where the plurality of bus addresses indicate physical locations of the data.

Communication between integrated graphics processing units

Performance of a computing system is improved by avoiding and/or eliminating overload conditions in storage systems. Performance utilization calculations are used to predict that a candidate placement configuration of storage resources within the storage systems will avoid overload conditions. The performance utilization calculations use performance profiles in conjunction with workload profiles to account for both storage system performance and actual workload traffic. Performance utilization calculations can also be used to report storage controller utilization information.

Storage resource management employing performance analytics

A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

Active non-volatile memory post-processing

Managing a network system includes determining metrics for a plurality of nodes in the network system, determining a plurality of zones including the plurality of nodes based on the metrics for the network system, and, for each zone of the plurality of zones, determining a computational architecture to be implemented for the zone based on the metrics for each node of the plurality of nodes in the zone.

Managing a network system

A method for cross-layer power management in a multi-layer system includes determining whether there is a service level violation for an application running on a hardware platform. Power consumption of the hardware platform is controlled in response to the service level violation.

Cross-layer power management in a multi-layer system

Elastic insight to Information Technology ('IT') performance data is provided. Local performance data is continuously pushed from a front-end component to a back-end component. Global performance data is continuously pushed from the back-end component to the front-end component. The local performance data and the global performance data are aggregated at the front-end component by product, product family, and product solution. The aggregated data is monitored at the front-end component to identify a performance bottleneck.

Providing elastic insight to information technology performance data

Probable anomalies associated with at least one data metric may be detected across a series of windows of time series data by comparison of data to a threshold. An estimated probability of anomalies for each of the windows of time series data may be determined based on the detected probable anomalies and the threshold. The windows of time series data may be ranked based on the estimated probabilities. Probable anomalies associated with highest ranked windows of time series data may be output to a user.

System and method for ranking anomalies

A system and methods for reliability management of virtual machines in a host system. The reliability of the host system is monitored and compared with a reliability threshold level for a virtual machine. If the reliability of the host system drops below the reliability threshold level, the virtual machine is migrated to another host system having an appropriate level of reliability.

Coordinated reliability management of virtual machines in a virtualized system

Illustrated is a system and method that includes a processor and service processor co-located on a common socket, the service processor to aggregate data from a distributed network of additional service processors and processors both of which are co-located on an additional common socket. The system and method also includes a first sensor to record the data from the processor. The system and method also includes a second sensor to record the data from a software stack. The system and method further includes a registry to store the data.

Managing sensor and actuator data for a processor and service processor located on a common socket

In a method of implementing a graph storage system, the graph storage system is stored on a plurality of computing systems. A global address space is provided for distributed graph storage. The global address space is managed with graph allocators, in which a graph allocator allocates space from a block of the distributed global memory in order to store a plurality of graphs.

Distributed graph storage system

In brief, the invention provides a method and system for admission control in a grid computing environment. When a user request for a global session is received from a submission node, applications to be launched through the global session are identified, and resource requirements are determined. A execution node is then allocated, and the global session is established between the execution node and the submission node. A user then requests an application session through the established global session, and the application session is established with the execution node.

Method and system using admission control in interactive grid computing systems

Growing community of inventors

Palo Alto, CA, United States of America

Vanish Talwar