Cadence Design Systems, Inc.

Vandana Gupta

Devendra Ramakant Deshpande

Sanjib Ghosh

Hitesh Marwah

Pawan Fangaria

Mahendra Singh Khalsa

Gerard Tarroux

Chun-Wen Chiang

Ashwani Kumar Sanwal

Sheng-Wei Lin

Embodiments disclosed are directed to systems and methods for modifying an electronic circuit design. According to embodiments, the method includes generating a circuit element of an electronic circuit layout on a graphical user interface, and generating an array group including a plurality of circuit elements. Each cell of the array group includes the same circuit element, and the array group is generated such that a change in at least one attribute of the array group is applied to each circuit element of the plurality of circuit elements.

System and method for repeating a synchronized set of layout geometries

The present embodiments relate to providing an overlap view of external and internal components of all instance circuit cells related to a master circuit cell in a same layout view. A layout of a circuit having a plurality of instance circuit cells of a master circuit cell is provided. Further, a graphical user interface including a user selectable option for an overlay view is provided. In addition, responsive to the selection of the overlay view, the plurality of instance circuit cells of the master circuit cell is determined. In addition, a plurality of sets of circuit elements, each set of circuit elements including external circuit elements that overlap with a corresponding instance circuit cell of the plurality of instance circuit cells is determined. Further, the plurality of sets of circuit elements overlaid on the master circuit cell is displayed on the layout view.

Editing of layout designs for fixing DRC violations

A circuit design process is presented that includes a block placement operation, followed by global routing based upon the initial placement of the blocks. Congestion data is generated from the global routing and, in an automated process, the blocks are placed again based upon the congestion data to reduce the routing congestion of the design. This can be used as part of a custom layout design process, for example.

Congestion aware block placement

A circuit design process for the reduction of routing congestion is described. This process includes a block placement operation, an initial pin optimization for the block placement, and global routing based upon the initial pin optimization. Congestion data is generated from the global routing and, in an automated process, the pins are re-optimized, based upon the congestion data. This process can be used as part of a custom layout design process, for example.

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Delhi, India

Vandana Gupta