Sandisk 3d LLC

Sandisk Technologies Inc.

Vance Dunton

Michael Konevecki

Natalie Nguyen

Raghuveer S Makala

Paul Wai Kie Poon

Steven J Radigan

Steve Radigan

Michael L Chan

Yung-Tin Chen

Luke Zhang

S Brad Herner

Usha Raghuram

Chuanbin Pan

Tong Zhang

Steven Patrick Maxwell

Yoichiro Tanaka

Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.

Vertical bit line non-volatile memory systems and methods of fabrication

A three-dimensional (3D) non-volatile memory array is provided having multiple word line layers stacked vertically with interleaving insulating layers over a vertically-oriented thin film transistor (TFT). The vertically-oriented TFT is used as a bit line selection device to couple a global bit line to a vertical bit line formed in a trench between portions of the word line and insulating layer stack. The word line layers are recessed horizontally to form recesses relative to the vertical bit line trench. The horizontal recesses provide spatial separation between memory cell areas and surfaces exposed during process steps. A memory material is formed conformally within the recesses, followed by a thin protective film. The film protects the memory material during etching to expose the vertical TFT for contact to the vertical bit line. Methods of fabricating arrays including recessed memory cell areas are provided.

Vertical bit line non-volatile memory with recessed word lines

A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.

Pillar devices and methods of making thereof

A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.

Patterning method for high density pillar structures

A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first conductivity type semiconductor layer in the plurality of openings, forming a second conductivity type semiconductor layer over the first conductivity type semiconductor layer in the plurality of openings, and selectively etching the second conductivity type semiconductor layer using an upper surface of the first conductivity type semiconductor layer as a stop to form a recess in the plurality of openings.

Method of making damascene diodes using selective etching methods

A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.

Method of making damascene diodes using sacrificial material

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San Jose, CA, United States of America

Vance Dunton