Agere Systems Inc.

Vance D Archer, Iii

Seung Hyuk Kang

Sailesh Mansinh Merchant

Taeho Kook

Daniel Patrick Chesire

Vivian Wanda Ryan

Warren K Gladden

Kouros Azimi

Kurt George Steiner

Mark Adam Bachman

Michael C Ayukawa

The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.

Routing under bond pad for the replacement of an interconnect layer

The invention, in one aspect, provides a semiconductor device (), including transistors (), dielectric layers () located over the transistors (), interconnects () formed within the dielectric layers (), and a test structure () located adjacent a hot-spot () of the semiconductor device () and configured to monitor a real-time operational parameter of at least one of the transistors () or interconnects ().

Thermal monitoring and management of integrated circuits

An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink

Integrated circuit device incorporating metallurigical bond to enhance thermal conduction to a heat sink

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Greensboro, NC, United States of America

Vance D Archer, Iii