Qualcomm Incorporated

Vanamali Bhat

Amod Phadke

Sina Dena

Xia Li

Bin Yang

Pankaj Deshmukh

Amit Aneja

Michael Tipton

Arun Sundaresan Iyer

Federico Salluzzo

Bharatheesha Sudarshan Jagirdar

Vishal Mishra

Vajram Ghantasala

Udayakiran Kumar Yallamaraju

Prachin Sheshrao Bhoyar

A method for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating is described. The method includes generating a set of clocks. The method also includes routing a selected one of the set of clocks for frequency measurement through one or more clock routing subsystems. The method further includes adjusting a frequency of the selected clock after the selected clock is routed through the clock routing subsystems. The method also includes communicating a sideband signal to indicate the adjusted frequency of the selected clock.

Clock monitoring subsystem for supporting dynamic frequency scaling and clock gating

A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.

Mitigation of duty-cycle distortion

An apparatus including a serial clock routing pipeline including a first set of clock inputs and a clock output; a first set of clock generators including a first set of clock outputs coupled to the first set of clock inputs of the serial clock routing pipeline, respectively; and a first clock monitoring unit including a first clock input coupled to the clock output of the serial clock routing pipeline, and a first status output to provide information concerning one or more of the first set of clock generators. The apparatus may further include a set of phase locked loops (PLLs) coupled to the set of clock generators, respectively; the set of PLLs also coupled to the clock monitoring unit.

Clock monitoring unit with serial clock routing pipeline

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Bengaluru, India

Vanamali Bhat