Cree Gmbh

Wolfspeed, Inc.

Van Mieczkowski

Helmut Hagleitner

Kevin Haberern

David T Emerson

Michael John Bergmann

Jonathan Young

Gerald H Negley

John Adam Edmond

David Beardsley Slater, Jr

Brian Thibeault

Jason Gurganus

John Williams Palmour

Qingchun Zhang

Mrinal Kanti Das

Scott Thomas Allen

Zoltan Ring

Daniel Namishia

Adam Barkley

William T Pulz

Brian Fetzer

Fabian Radulescu

Terry Alcorn

Kevin W Haberern

David Todd Emerson

A Schottky diode is disclosed that includes a silicon carbide substrate, a silicon carbide drift layer, a Schottky contact, and a passivation structure. The silicon carbide drift layer provides an active region and an edge termination region about the active region. The Schottky contact has sides and a top extending between the two sides and includes a Schottky layer over the active region and an anode contact over the Schottky layer. The passivation structure covers the edge termination region, the sides of the Schottky contact, and at least a portion of the top of the Schottky contact. The passivation structure includes a first silicon nitride layer, a silicon dioxide layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon dioxide layer.

Passivation structure for semiconductor devices

A power module includes a first terminal, a second terminal, and a number of semiconductor die coupled between the first terminal and the second terminal. The semiconductor die are configured to provide a low-resistance path for current flow from the first terminal to the second terminal during a forward conduction mode of operation and a high-resistance path for current flow from the first terminal to the second terminal during a forward blocking configuration. Due to improvements made to the power module, it is able to pass a temperature, humidity, and bias test at 80% of its rated voltage for at least 1000 hours.

Power module with improved reliability

The present disclosure relates to providing via plugs in vias of a semiconductor material. The via plugs may be formed of a polymer, such as a polyimide, that can withstand subsequent soldering and operating temperatures. The via plugs effectively fill the vias to prevent the vias from being filled substantially with solder during a subsequent soldering processes.

Polymer via plugs with high thermal integrity

The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.

Contact pad

Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.

Wafer-level die attach metallization

A high voltage semiconductor device can include a high voltage semiconductor device package that includes a wall defining a recess within the high voltage semiconductor device package. A high voltage semiconductor chip can be in the recess and a high voltage electric arc suppression material can be in the recess.

High voltage semiconductor devices including electric arc suppression material and methods of forming the same

Semiconductor Schottky barrier devices include a wide bandgap semiconductor layer, a Schottky barrier metal layer on the wide bandgap semiconductor layer and forming a Schottky junction, a current spreading layer on the Schottky barrier metal layer remote from the wide bandgap semiconductor layer and two or more diffusion barrier layers between the current spreading layer and the Schottky barrier metal layer. The first diffusion barrier layer reduces mixing of the current spreading layer and the second diffusion barrier layer at temperatures of the Schottky junction above about 300&#xb0; C. and the second diffusion barrier layer reduces mixing of the first diffusion barrier layer and the Schottky barrier metal layer at the temperatures of the Schottky junction above about 300&#xb0; C.

Multilayer diffusion barriers for wide bandgap Schottky barrier devices

Wide bandgap semiconductor devices are fabricated by providing a wide bandgap semiconductor layer, providing a plurality of recesses in the wide bandgap semiconductor layer, and providing a metal gate contact in the plurality of recesses. A protective layer may be provided on the wide bandgap semiconductor layer, the protective layer having a first opening extending therethrough, a dielectric layer may be provided on the protective layer, the dielectric layer having a second opening extending therethrough that is narrower than the first opening, and a gate contact may be provided in the first and second openings. The metal gate contact may be provided to include a barrier metal layer in the plurality of recesses, and a current spreading layer on the barrier metal layer remote from the wide bandgap semiconductor layer. Related devices and fabrication methods are also discussed.

Semiconductor devices having improved adhesion and methods of fabricating the same

Schottky barrier semiconductor devices are provided including a wide bandgap semiconductor layer and a gate on the wide bandgap semiconductor layer. The gate includes a metal layer on the wide bandgap semiconductor layer including a nickel oxide (NiO) layer. Related methods of fabricating devices are also provided herein.

Semiconductor devices having gates including oxidized nickel

An apparatus that comprises a device on a substrate and a crack stop in the substrate. Methods of forming a device are also disclosed. The methods may include providing a device, such as a semiconductor device, on a substrate having a first thickness, reducing the thickness of the substrate to a second thickness, and providing a crack stop in the substrate. Reducing the thickness of the substrate may include mounting the substrate to a carrier substrate for support and then removing the carrier substrate. The crack stop may prevent a crack from reaching the device.

Devices with crack stops

The present disclosure relates to a thin film resistor that is formed on a substrate along with other semiconductor devices to form all or part of an electronic circuit. The thin film resistor includes a resistor segment that is formed over the substrate and a protective cap that is formed over the resistor segment. The protective cap is provided to keep at least a portion of the resistor segment from oxidizing during fabrication of the thin film resistor and other components that are provided on the semiconductor substrate. As such, no oxide layer is formed between the resistor segment and the protective cap. Contacts for the thin film resistor may be provided at various locations on the protective cap, and as such, are not provided solely over a portion of the resistor segment that is covered with an oxide layer.

Thin film resistor

Light emitting devices include an active region of semiconductor material and a first contact on the active region. The first contact is configured such that photons emitted by the active region pass through the first contact. A photon absorbing wire bond pad is provided on the first contact. The wire bond pad has an area less than the area of the first contact. A reflective structure is disposed between the first contact and the wire bond pad such that the reflective structure has substantially the same area as the wire bond pad. A second contact is provided opposite the active region from the first contact. The reflective structure may be disposed only between the first contact and the wire bond pad. Methods of fabricating such devices are also provided.

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Apex, NC, United States of America

Van Mieczkowski