Advanced Micro Devices Corporation

Van Hung Pham

Nguyen Duc Bui

Amit P Marathe

John T Yue

Sunil D Mehta

Xiao-yu Li

Michael Anthony Niederhofer

A method and apparatus for monitoring and controlling integrated circuit devices-under-test (DUTS). A preferred embodiment includes a computer based controller, a temperature control module, a power supply controller, a chamber interface module, a driver card and a DUT board. The computer-based controller responding to preprogrammed instructions (software) operates and coordinates the temperature control module, the chamber interface module, the power supply controller, and the driver card. The driver card, receiving commands and data from the computer-based controller, sends and receives a number of signals to and from the DUTs on the DUT board. These signals include voltage sources for operating the DUTs, a load voltage, DC current sources for setting duty and frequency cycles, switch signals, voltage measurement signals, and resistance measurement signals. The DUT board is a printed circuit board for holding a number of DUTs. Each of the DUTs is an integrated circuit containing one or more sets of circuitry for testing specifically designed test structures.

Method and apparatus for reliability testing of integrated circuit structures and devices

A categorization of a particular semiconductor wafer based on void size is obtained from sigma data and T0.1% failure data that has been obtained from wafers subjected to isothermal testing. The sigma data and the T0.1% failure data for the particular wafer is compared to stored data corresponding to ranges for sigma and T0.1% data for each of a plurality of void categories, and the particular wafer is categorized based on the stored data. The T0.1% failure data is computed based on a T50% failure data and the sigma value, so that small sample sizes can be utilized to obtain the stored data.

Sensitive technique for metal-void detection

A multi-level metal interconnect structure in a semiconductor device includes a plurality of overlying metal layers separated by ILD layers and electrically connected by filled vias in the ILD layers. Each metal layer includes a relatively thick antireflective layer for improved electromigration resistance. Each metal layer also includes a metal lining layer and a metal interconnect layer overlying the metal lining layer. Enhanced electromigration resistance is obtained by forming the antireflective layer to a thickness of no less than the thickness of the metal lining layer. In a preferred embodiment of the invention, the antireflective layer has a thickness of about 1000 angstroms.

Semiconductor device having a multi-layer metal interconnect structure

A substantially constant current is conducted in a first direction through an interconnect structure having a barrier layer to determine the lifetime of the structure in the first current direction. A substantially identical current is conducted in a second direction through a substantially identical interconnect structure to determine the lifetime of the structure in the second current direction. These tests are repeated for identical structures but having different barrier layer thicknesses. The results of these lifetime tests are compared to determine the barrier layer's effect on electromigration in the structure, which can be used to design the barrier layer to optimize the structure's lifetime and speed.

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Milpitas, CA, United States of America

Van Hung Pham