International Business Machines Corporation

Other

Van Hoa Lee

David R Willoughby

George John Dawkins

Kiet Anh Tran

David Dean Sanner

Thi Ngoc Tran

David Lee Randall

Tam D Bui

Steven Paul Hartman

Kanisha Patel

Eric A Hudson

Robert Christopher Dixon

Gordon David McIntosh

Thoi Nguyen

Robert Kimberlin Foster

Milton Devon Miller, Ii

Christopher Harry Austen

Ashwini Kulkarni

Richard Louis Arndt

Louis Bennie Capps, Jr

Charles Andrew McLaughlin

Shaival Jagdishbhai Chokshi

Stephen Joseph Schwinn

Priya Paul

Jayeshkumar M Patel

Douglas Wayne Oliver

Alan Hlava

Prakash Vinodrai Desai

Quan Wang

Casey Lee McCreary

Sayileela Nulu

Timothy Albert Smith

Natalie Marie Post

Peter Dinh Phan

A device for use during fishing configured to be connected to the user's fishing line to attract fish. The device is shaped to be moved through the water and generally include a head and a tail. A channel extends through at least a portion of the device and is sized to receive the fishing line. The device is constructed from multiple sections. The sections are selectively positionable between a closed configuration with the sections connected together to connect the device to the fishing line, and an open configuration with the sections being separated to remove the device from the fishing line.

Multi-section fishing device

Embodiments of the present invention provide a method for initializing a plurality of processors of a multi-processor system by executing, at each respective processor of the plurality of processors, at least a portion of local initialization code stored on the respective processor. Receiving, at a designated processor of the plurality of processors, external initialization code stored in external memory, wherein the remainder of the plurality of processors do not have access to the external initialization code stored in external memory. Determining, the designated processor, send at least a portion of the external initialization code to a processor of the remainder of the plurality of processors.

Selection of a primary microprocessor for initialization of a multiprocessor system

Disclosed is a computer implemented method, computer program product, and apparatus for generating diagnostic data for a thread. A service processor may begin by executing the computer usable program code to allocate a first thread to a monitoring function. The service processor determines if a second thread is running, wherein the second thread is associated with an operation. The service processor obtains an object pointer from a list of running threads, wherein the object pointer references a time data structure associated with the second thread, the time data structure comprising a maximum running time interval and a check time. The service processor calculates the check time as a maximum running time interval added to an initially sampled timestamp. The service processor determines if a current time exceeds the check time. In addition, the service processor generates an error log, responsive to a determination that the current time exceeds the check time.

Generate diagnostic data for overdue thread in a data processing system

Illustrative embodiments manage deadlock in a data processing system during an IPL process that includes monitoring the usage of locks in the Hardware Object Model (HOM) of the data processing system. The process further includes detecting a deadlock condition in response to an indication of the IPL process in the data processing system entering a hung state when at least one lock is in use. The process also includes handling the deadlock condition by performing one or more of the following: recording error information for the deadlock condition, and terminating the IPL process.

Detecting a deadlock condition by monitoring firmware inactivity during the system IPL process

An event manager can be used to effect a library function call from a caller service processor application to a data processing function in a library. The library is compiled into a callee service processor application, including passing, by the caller service processor application to the event manager through the caller service processor application's API, an event representing the library function call; passing, by the event manager to the callee service processor application, the event representing the library function call; executing by the callee service processor application the library function call, including retrieving return data from the library function call; returning, by the callee service processor application to the event manager, an event representing the return data from the library function call; and returning, by the event manager to the caller service processor application, the event representing the return data from the library function call.

Using an event manager to effect a library function call

A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching. A page is reserved in system memory. This reserved page is made unavailable to the operating system and may not be utilized by any software in the system. The reserved page is also written with all bytes set to 0xFF. The system firmware then selects a region in system memory for the TCE table. The TCE table is initialized, with all entries within the TCE table initialized to be valid and contain the corresponding address of the reserved page.

Data processing system and computer program product to allow PCI host bridge (PHB) to handle pre-fetch read transactions on the PCI bus which access system memory through translation control entry (TCE) table

A method, system, and computer instructions for changing the lock-bits combination used to lock a resource upon receiving a system reset exception. The present invention forces the software to use different lock-bits combinations based on the number of occurrences of system reset exceptions. When a system reset exception is received, a system reset exception bit value in a special purpose register is updated based on the history of system reset exception occurrences. Based on the updated value in the system reset exception bit, the lock-bits combination for locking a resource is changed to allow the data processing system to reuse the resource with bad lock-bits. In this manner, the deadlocked resource is resolved, and a processor is not able to obtain an indefinitely held lock on system resources caused by system reset exceptions.

Method to switch the lock-bits combination used to lock a page table entry upon receiving system reset exceptions

A method, computer program product, and a data processing system for maintaining operation of the data processing system in the event of a degraded system cooling condition is provided. A first temperature of a processor is identified as equaling or exceeding a processor throttling threshold. The operational frequency of the processor is reduced by a first frequency increment. The operational voltage of the processor is then reduced by a first voltage increment. Updated values of the processor temperature are periodically obtained and continued reductions in the frequency and operational voltage are made until the temperature indicates that the processor is operating in a stable throttle range. The frequency and operational voltage of the processor may be returned to normal levels when an updated temperature of the processor is less or equal to a throttle off threshold.

System and method to maintain data processing system operation in degraded system cooling condition

A method, apparatus, and computer instructions for managing a set of processors. In response to a request to deallocate a processor assigned to a partition within the logical partitioned data processing system, the processor in the set of processors, is stopped. In response to stopping the processor, the processor is placed in an isolated state in which the processor is isolated from the partition. The processor is then placed in a pool of resources for later reassignment.

Method and apparatus for dynamically allocating and deallocating processors in a logical partitioned data processing system

A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating system run by a processor configured to support logical partitioning is virtualized to produce a first logical address range. A second physical address range allocated for system memory for the operating system is virtualized to produce a second logical address range. The first physical address range and the second physical address range are non-contiguous. Virtualization of the first and second physical address ranges is had such that the first logical address range and the second logical address range are contiguous. A memory mapped input/output physical address range that is intermediate the first physical address range and the second physical address range is virtualized to produce a third logical address range. A lowermost logical address of the third logical address range exceeds a respective upper most logical address of the first and second logical address ranges.

Data processing system and computer program product for support of system memory addresses with holes

A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching. The mechanism of the present invention reserves a page in system memory. This reserved page is made unavailable to the operating system and may not be utilized by any software in the system. The reserved page is also written with all bytes set to 0xFF. The system firmware then selects a region in system memory for the TCE table. The TCE table is initialized, with all entries within the TCE table initialized to be valid as well as contain the corresponding address of the reserved page. In this manner, all supported DMA page addresses will have valid TCE entries which translate the DMA addresses into the reserved page memory. Thus, prefetched DMA addresses will not encounter invalid DMA address translation, and crash the system.

Method to allow PCI host bridge (PHB) to handle pre-fetch read transactions on the PCI bus which access system memory through translation control entry (TCE) table

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Cedar Park, TX, United States of America

Van Hoa Lee