Broadcom Corporation

Vamsi M Tatapudi

Philip H Chen

Chien-Hsien Wu

Anirban Banerjee

Brandon Carl Smith

John Jeffrey Dull

Nithyananda Miyar

Shashi S Math

A hash table supports extended entries. The extended entries permit a base entry to extend its associated data into one or more neighboring entries. Extended entries thereby provide a mechanism through which a hash table entry may store additional data compared to a base entry. Extended entries may coexist with base entries in the hash table. The hash table thereby provides the flexibility to adapt dynamically to meet system requirements and to balance the needs of additional data storage by blending the number of extended entries (that each store more data than a base entry) and the number of base entries (each storing less data than an extended entry).

Extended width entries for hash tables

The present invention is directed to a network device, method and apparatus for processing data. The present invention includes at least one ingress module for performing switching functions on incoming data. The invention further includes a memory management unit (MMU) for storing the incoming data, and at least one egress module for transmitting the incoming data to at least one egress port. Further, in the present invention, the memory management unit further comprises a cell copy count pool (CCP) memory, wherein the CCP determines when a memory cell can be made available.

Cell copy count

A programmable network component for use in a plurality of network devices with a shared architecture, where the programmable network component includes an interface with an external processing unit to provide management interface control between the external processing unit and a network device. The programmable network component also includes a plurality of internal busses each of which is coupled to the programmable network component and to at least one network component. The programmable network component further includes a plurality of external buses each of which is coupled to the programmable network component and to at least one physical interface. The programmable network component is configured to support a plurality of protocols for communication with a plurality of physical interface components and comprises a plurality of programmable registers for determining the status of the plurality of physical interfaces.

Method and apparatus for dynamically configuring hardware resources by a generic CPU management interface

Cell copy count hazard detection

A switching chip for performing switching and other functions on packets transmitted through the switching chip. The switching chip includes a memory management unit that identifies a class of service to which each packet belongs, wherein upon processing the packet. The memory management unit transmits the packet to a CPU through a CPU processing module. The switching chip also includes a CPU processing module that includes a class of service bitmap that is associated with a plurality of channels. Each of the plurality of channels is further associated with at least one class of service, includes a per channel bit and is assigned a predefined priority level. Upon receiving packets from the memory management unit, the CPU processing module is configured to sort the packets according to the class of service to which the packet belongs and store each packet in an associated one of the plurality of channels. The CPU processing module is also configured to use the per channel bit to determine how to process packets in each for the plurality of channels for which there is no available CPU buffer. When there is no available CPU buffer for one of the plurality of channels, the CPU processing module is configured to set an appropriate bit in the class of service bitmap and transmits the class of service bitmap to the memory management unit.

Method and apparatus for direct memory access based on class-of-service

A network device for processing packets. The network device includes a CPU processing module for transmitting information between at least one memory location on the network device and an external CPU memory location. The CPU processing module includes a first engine for performing bulk transfer of information from the at least one memory location on the network device to the external CPU memory location, wherein all entries of the at least one memory location on the network device are transferred to the external CPU memory location, and a second engine for performing bulk transfer of information from the external CPU memory location to at least one memory location on the switching chip, wherein a plurality of entries from the external CPU memory location is transferred to the memory locations on the switching chip. The second engine uses a bit received from a CPU to determine how entries will be added in the at least one memory location on the switching chip.

Growing community of inventors

Santa Clara, CA, United States of America

Vamsi M Tatapudi