International Business Machines Corporation

Globalfoundries Inc.

Other

Canon Anelva Corporation

Vamsi Krishna Paruchuri

Vijay Narayanan

Bruce Bennett Doris

Eduard Albert Cartier

Rajarao Jammy

Michael Patrick Chudzik

Martin Michael Frank

Supratik Guha

Barry P Linder

Hemanth Jagannathan

Cyril Cabral, Jr

Matthew Warren Copel

Evgeni Petrovich Gousev

Michelle Leigh Steen

Dae-Gyu Park

Paul Charles Jamison

Alessandro Cesare Callegari

Nestor A Bojarczuk, Jr

Young-hee Kim

Lisa F Edge

Veeraraghavan S Basker

Son Van Nguyen

Hariklia Deligianni

Sufi Zafar

Naim Moumen

Rashmi Jha

Keith Kwong Hon Wong

Alfred Grill

Hosadurga K Shobha

Tze-Chiang Chen

Seth L Knupp

Alexander Reznicek

Takashi Ando

Theodorus E Standaert

Jeffrey W Sleight

Guy M Cohen

Ying Di Zhang

Arvind Kumar

Deepika Priyadarshini

Young-Hee Kim

Michael Abramovich Gribelyuk

Tuan Anh Vo

Patricia May Mooney

Changhwan Choi

Chih-Chao Yang

Ghavam G Shahidi

Daniel C Edelstein

Clement Hsingjen Wann

Yun Yu Wang

Sivananda K Kanakasabapathy

Takeshi Nogami

Katherine Lynn Saenger

Dominic Joseph Schepis

Herbert Lei Ho

Renee Tong Mo

Huiming Bu

Siddarth A Krishnan

Emanuel Israel Cooper

Sunfei Fang

Xiaoyan Shao

Sebastian Naczas

Chester T Dziobkowski

Mark J Hurley

Kangguo Cheng

Ali Khakifirooz

Juntao Li

William R Tonti

Toshiharu Furukawa

Richard Stephan Wise

John Michael Cotte

Lubomyr Taras Romankiw

Balasubramanian S Haran

Richard Alan Haight

John Christopher Arnold

James N Pan

Wei Lin

Kathryn Turner Schonenberg

Hongwen Yan

Xi Li

Nestor Alexander Bojarczuk, Jr

Siva Kanakasabapathy

Stephen L Brown

Martin Patrick O'Boyle

Philippe M Vereecken

Glenn A Biery

Joseph S Newbury

Edmund M Sikorski

Mark Todhunter Robson

Philippe Mark Vereecken

Russell D Allen

Takaaki Tsunoda

Sanjay Shinde

Elizabeth A Duch

Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.

Ultrathin multilayer metal alloy liner for nano Cu interconnects

An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.

Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments

Complementary metal oxide semiconductor replacement gate high-K metal gate devices with work function adjustments

A method of forming electrically conductive structures that includes forming a copper containing layer including a barrier forming element, and applying a first anneal to the copper containing layer. The first anneal increases grain size of the copper in the copper containing layer. The copper containing layer is etched to provide a plurality of copper containing lines. A dielectric fill is deposited in the space between adjacent copper containing lines. A second anneal is applied to the plurality of copper containing lines. During the second anneal the barrier forming element diffuse to an interface between sidewalls of the copper containing lines and the dielectric fill to form a barrier layer along the sidewalls of the copper containing lines.

Self-forming barrier for subtractive copper

Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV.

Replacement gate electrode with multi-thickness conductive metallic nitride layers

A method is provided for forming a fin cut that enables a single diffusion break in very dense CMOS structures formed using bulk semiconductor substrates. A dummy gate is removed from a finned structure to expose the top regions of the fins, the bottom fin regions being within a shallow trench isolation region. Selective vapor phase etching follows sequential ion implantation of the top and bottom fin regions to form a diffusion break cut region. The non-implanted regions of the substrate and the shallow trench isolation region remain substantially intact during each etching procedure. Double diffusion break cut regions are also enabled by the method.

Fin cut enabling single diffusion breaks

Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.

Changing effective work function using ion implantation during dual work function metal gate integration

An apparatus and method bond a first wafer to a second wafer. The apparatus includes a first pressure application device configured to apply pressure at a central region of the first wafer in a direction toward the second wafer to initiate a bonding process between the first wafer and the second wafer. The apparatus also includes one or more second pressure application devices configured to apply pressure between the central region and an outer edge of the first wafer to complete the bonding process. The one or more second pressure application devices apply pressure on the first wafer after the first pressure application device has initiated the bonding process and while the first pressure application device continues to apply pressure at the central region. A controller controls the first pressure application device and the one or more second pressure application devices.

Wafer bonding for 3D device packaging fabrication

A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.

Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings

Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

High-K/metal gate stack using capping layer methods, IC and related transistors

Growing community of inventors

New York, NY, United States of America

Vamsi Krishna Paruchuri