Agilent Technologies, Inc.

Vamsi K Srikantam

Dietrich Werner Vook

Andrew David Fernandez

Thomas Edward Kopley

Paul Lewis Corredoura

Airell Richard Clark, Ii

Kenneth D Poulton

Robert M R Neff

Mario Martinez

Andew David Fernandez

An upconverting circuit is disclosed. The upconverting circuit includes a polyphase component generator that provides Npolyphase components at each input polyphase cycle, wherein N&#x3e;2 on each input polyphase cycle defined by a clock. A memory stores the polyphase components from at least one polyphase cycle prior to the current polyphase cycle. A plurality of filters process the polyphase components stored in the memory. Each filter processes a plurality of the polyphase components to generate a filtered polyphase component corresponding to that filter. A multiplexer outputs the filtered polyphase components in a predetermined order to generate a filtered output signal. In one embodiment, each filter utilizes the same functional relationship to generate the filtered polyphase components. In another embodiment, the memory is a shift register. The filters can be of arbitrary complexity.

Digital modulator employing a polyphase up-converter structure

Generally, the embodiments presented are directed to circuits and methods for triggering an event at a fraction of a clock cycle. A triggering circuit can comprise two or more input circuits that output an event signal. The event signal is received by one of two or more delay circuits that trigger the event signal at a predetermined phase of the clock cycle by moving the event signal from a first clock domain to another clock domain. By triggering the event at a phase division, the triggering circuit outputs signals at a rate faster than the clock cycle.

Triggering events at fractions of a clock cycle

Generally, the embodiments are directed to circuits and methods for time stamping an event at a fraction of a clock cycle. A time stamping circuit comprises two or more detection circuits. The detection circuits receive an event-in signal and generate event signals based on a clock phase at which the event-in signal was received. A decoder receives the event signals and outputs an event-out signal and a time stamp that represents the phase at which the event-in signal was detected. By time stamping the event-in signal to a phase division, the time stamping circuit detects event signals that occur at a rate faster than the clock cycle.

Time stamping events for fractions of a clock cycle

A method for calibrating time interleaved samplers comprising applying a calibration signal to a time-interleaved sampling device, wherein the signal is coherent with at least one sample clock on the device and is periodic and has a predetermined spectral content and frequency, sampling, by said time-interleaved sampling device, the calibration signal at a plurality of phases to form samples, averaging the formed samples, and calculating the phase error of each sample based on the average calibration signal sample.

System and method for timing calibration of time-interleaved data converters

The method defines an input state vector that achieves low power consumption when applied to the circuit inputs of a digital circuit in an idle state. The digital circuit includes one or more circuit elements of respective circuit element types. In the method, idle power values including idle power values for each circuit element type. The idle power values for each circuit element type correspond to different states of the inputs of a circuit element of the circuit element type. Additionally the idle power values are used to determine, for each circuit element, states of the inputs of the circuit element that would set the circuit element to a lowest-allowable idle power state when the digital circuit is in the idle state. The states determined for those of the inputs that constitute the circuit inputs define the input state vector. The states are also determined accounting for the logic constraints of the digital circuit.

Method and apparatus for defining an input state vector that achieves low power consumption in digital circuit in an idle state

The method defines an input state vector that achieves low power consumption when applied to the circuit inputs of a digital circuit in an idle state. In the method, independent determinations are performed. Each determination defines a respective set of the input states of the input state vector. Any conflict the definitions of any one or more of the input states is resolved in favor of the definition of the one or more of the input states that achieves the lowest idle power consumption when the input state vector incorporating the one or more of the input states in accordance with the definition is applied to the circuit inputs of the digital circuit in the idle state.

Method and apparatus for defining an input state vector that achieves low power consumption in a digital circuit in an idle state

A clock gating circuit reduces the power dissipation in a digital circuit including at least one functional block by gating the clock signal at an input to a clock tree feeding the functional block. The clock gating circuit includes a logic gate that receives a clock signal and a clock disable signal generated by the functional block, and gates the clock signal at the input to the clock tree feeding the functional block. Further, a global signal generator is provided to transmit a global signal to each of the functional blocks to prevent the generation of clock disable signals, when necessary, such as during testing of chips.

Method and apparatus for clock gating clock trees to reduce power dissipation

A circuit design system that obtains low power circuit design through judicious module selection. The circuit design system implements methods that enable advantageous design tradeoffs between low power behavior and a set of design constraints during module selection. The circuit design system selects unsigned modules which consume less power than signed modules where permitted in view of a desired response of a circuit and where advantageous for low power behavior while not violating the design constraints.

Low power circuit design through judicious module selection

A flip-flop having a sleep mode in which power consumption is reduced. The flip-flop comprises a clock input, a data input, an input stage, an input gate, an output stage and an output clamp. The input gate is interposed between the data input and the input stage and operates in the sleep mode to isolate the input stage from the data input. The output stage is coupled to the input stage and includes an output having a first output state and a second output state. The output clamp operates in the sleep mode to set the output stage to a predetermined state regardless of the data states at the data input and the clock input. The predetermined state is the one of the output states in which the leakage power consumption of the flip-flop is less than in the other of the output states. The predetermined state may alternatively be the one of the output states in which the leakage power consumption of circuitry connected to the output of the flip-flop is less than in the other of the output states. As a further alternative, the predetermined state may be the one of the output states in which the leakage power consumption of a digital electronic circuit of which the flip-flop forms part is less than in the other of the output states.

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Sunnyvale, CA, United States of America

Vamsi K Srikantam