Intel Corporation

Nanochip, Inc.

Valluri Ramana Rao

Qing Ma

Li-Peng Wang

Johanna M Swan

Telesphor Kamgaing

Feras Eid

Andrew A Berlin

Richard H Livengood

Mineo Yamakawa

Adel A Elsherbini

Peng Cheng

Quan Anh Tran

Han Wui Then

Baris Bicen

John Heck

Marko Radosavljevic

Sansaptak W Dasgupta

Aleksandar Aleksov

Shawna M Liff

Georgios C Dogiamis

Sasha N Oster

Vijay K Nair

Thomas L Sounart

Robert S Chau

Yuegang Zhang

Robert L Sankman

Mario J Paniccia

Tsung-Kuan Allen Chou

Paul Winer

Jeffrey K Greason

Gabi Neubauer

Dong S Shim

Ravi Pillarisetty

Patrick R Morrow

Paul B Fischer

Kimin Jun

Steven J Kirch

Andreas Duevel

Kevin Lai Lin

Weng Hong Teh

Issy Kipnis

Uwe Zillmann

Krishnamurthy Murali

Daniel M Wong

Jack T Kavalieros

Gilbert W Dewey

Ian A Young

Niloy Mukherjee

Stefan Rusu

Rishabh Mehandru

Kevin O'Brien

Ofir Degani

Gerhard Schrom

Kramadhati V Ravi

Bruce A Block

Chien Chiang

Nathan Franklin

Simon M Tam

Doug B Ingerly

Jose A Maiz

Narayanan Sundararajan

Greg Atwood

Eyal Bar-sadeh

Bala Natarajan

William Baerg

Byong Man Kim

Oing Ma

Steve Seidel

Mark T Bohr

Xing Su

Szuya S Liao

Paul A Koning

Roza Kotlyar

Fay Hua

Harish Krishnamurthy

Selena Chan

Albert Fazio

Georgios Yorgos Palaskas

Robert J Chen

Ruchir Saraswat

Peter G Tolchinsky

Andre Schaefer

Thomas P Thomas

Sanjay Rangan

Tak Ming Mak

Ajay Jain

Christopher M Pelto

Donald E Adams

Robert N Stark

Jun Su

C Michael Garner

Stefan K Lai

John Magana

Michael DiBattista

Bryan M White

Michele J Berry

Yorgos Palaskas

Yevgeny Anoikin

Goutam Paul

Uwe Zillman

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

Integrated circuit device structures and double-sided electrical testing

System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Fand also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

Group III-N transistors for system on chip (SOC) architecture integrating power management and radio frequency circuits

Embodiments of the invention include an active fiber with a piezoelectric layer that has a crystallization temperature that is greater than a melt or draw temperature of the fiber and methods of forming such active fibers. According to an embodiment, a first electrode is formed over an outer surface of a fiber. Embodiments may then include depositing a first amorphous piezoelectric layer over the first electrode. Thereafter, the first amorphous piezoelectric layer may be crystallized with a pulsed laser annealing process to form a first crystallized piezoelectric layer. In an embodiment, the pulsed laser annealing process may include exposing the first amorphous piezoelectric layer to radiation from an excimer laser with an energy density between approximately 10 and 100 mJ/cm2 and pulse width between approximately 10 and 50 nanoseconds. Embodiments may also include forming a second electrode over an outer surface of the crystallized piezoelectric layer.

Inorganic piezoelectric materials formed on fibers and applications thereof

Embodiments of the present disclosure describe techniques for fabricating a stacked integrated circuit (IC) device. A first wafer that includes a plurality of first IC dies may be sorted to identify first known good dies of the plurality of first IC dies. The first wafer may be diced to singulate the first IC dies. A second wafer that includes a plurality of second IC dies may be sorted to identify second know good dies of the plurality of second IC dies. The first known good dies may be bonded to respective second known good dies of the second wafer. In some embodiments, the first known good dies may be thinned after bonding the first know good dies to the second wafer. Other embodiments may be described and/or claimed.

Techniques for die stacking and associated configurations

Embodiments of the invention include a display formed on an organic substrate and methods of forming such a device. According to an embodiment, an array of pixel mirrors may be formed on the organic substrate. For example, each of the pixel mirrors is actuatable about one or more axes out of the plane of the organic substrate. Additionally, embodiments of the invention may include an array of routing mirrors formed on the organic substrate. According to an embodiment, each of the routing mirrors is actuatable about two axes out of the plane of the organic substrate. In embodiments of the invention, a light source may be used for emitting light towards the array of routing mirrors. For example, light emitted from the light source may be reflected to one or more of the pixel mirrors by one of the routing mirrors.

Adaptable displays using piezoelectric actuators

Disclosed herein are maskless imaging tools and display systems that include piezoelectrically actuated mirrors and methods of forming such devices. The maskless imaging tool may include a light source. Additionally, the tool may include one or more piezoelectrically actuated mirrors for receiving light from the light source. The piezoelectrically actuated mirrors are actuatable about one or more axes to reflect the light from the light source to a workpiece positioned to receive light from the piezoelectrically actuated mirror. Disclosed herein is a maskless imaging tool that is a laser direct imaging lithography (LDIL) tool. The maskless imaging tool may also be a via-drill tool. Disclosed herein is also a piezoelectrically actuated mirror used in a projection system. For example, the projection system may be integrated into a pair of glasses.

Piezo actuators for optical beam steering applications

Embodiments of the invention include a piezo-electric mirror in an microelectronic package and methods of forming the package. According to an embodiment the microelectronic package may include an organic substrate with a cavity formed in the organic substrate. In some embodiments, an actuator is anchored to the organic substrate and extends over the cavity. For example, the actuator may include a first electrode and a piezo-electric layer formed on the first electrode. A second electrode may be formed on the piezo-electric layer. Additionally, a mirror may be formed on the actuator. Embodiments allow for the piezo-electric layer to be formed on an organic package substrate by using low temperature crystallization processes. For example, the piezo-electric layer may be deposited in an amorphous state. Thereafter, a laser annealing process that includes a pulsed laser may be used to crystallize the piezo-electric layer.

Process for creating piezo-electric mirrors in package

A complementary metal oxide semiconductor (CMOS) device that includes a gallium nitride n-type MOS and a silicon P-type MOS is disclosed. The device includes silicon 111 substrate, a gallium nitride transistor formed in a trench in the silicon 111 substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode. The device further includes a silicon/polysilicon layer formed over the gallium nitride transistor.

Gallium nitride NMOS on Si (111) co-integrated with a silicon PMOS

Embodiments of the invention include a piezoelectric package integrated filtering device that includes a film stack. In one example, the film stack includes a first electrode, a piezoelectric material in contact with the first electrode, and a second electrode in contact with the piezoelectric material. The film stack is suspended with respect to a cavity of an organic substrate having organic material and the film stack generates an acoustic wave to be propagated across the film stack in response to an application of an electrical signal between the first and second electrodes.

Piezoelectric package-integrated film bulk acoustic resonator devices

Embodiments of the invention include a filtering device that includes a first electrode, a piezoelectric material in contact with the first electrode, and a second electrode in contact with the piezoelectric material. The piezoelectric filtering device expands and contracts laterally in a plane of an organic substrate in response to application of an electrical signal between the first and second electrodes.

Piezoelectric package-integrated contour mode filter devices

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

Integrated circuit structures

Embodiments of the invention include an optical routing device that includes an organic substrate. According to an embodiment, an array of cavities are formed into the organic substrate and an array of piezoelectrically actuated mirrors may be anchored to the organic substrate with each piezoelectrically actuated mirror extending over a cavity. In order to properly rout incoming optical signals, the optical routing device may also include a routing die mounted on the organic substrate. The routing die may be electrically coupled to each of the piezoelectrically actuated mirrors and is able to generated a voltage across the first and second electrodes of each piezoelectrically actuated mirror. Additionally, a photodetector may be electrically coupled to the routing die. According to an embodiment, an array of fiber optic cables may be optically coupled with one of the piezoelectrically actuated mirrors and optically coupled with the photodetector.

Piezoelectrically actuated mirrors for optical communications

The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.

Multi-layer silicon/gallium nitride semiconductor

This disclosure is directed to a complementary metal oxide semiconductor (CMOS) transistor that includes a gallium nitride n-type MOS and a silicon P-type MOS. The transistor includes silicon 111 substrate, a gallium nitride transistor formed in a trench in the silicon 111 substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode; a polysilicon layer formed on the gallium nitride transistor, the polysilicon layer coplanar with a top side of the silicon 111 substrate; a first metal via disposed on the source electrode; a second metal via disposed on the gate electrode and isolated from the first metal via by a polysilicon layer; a first trench contact formed on the first metal via; and a second trench contact formed on the second metal via; the first trench contact isolated from the second trench contact by at least one replacement metal gate (RMG) polysilicon island.

Embodiments of an embedded mm-wave radio integrated circuit into a substrate of a phased array module are disclosed. In some embodiments, the phased array module includes a first set of substrate layers made of a first material. The mm-wave radio integrated circuit may be embedded in the first set of substrate layers. A second set of substrate layers may be coupled to the first set of substrate layers. The second set of substrate layers may be made of a second material that has a lower electrical loss than the first material. The second set of substrate layers may include a plurality of antenna elements coupled through vias to the mm-wave radio integrated circuit.

Embedded millimeter-wave phased array module

Growing community of inventors

Saratoga, CA, United States of America

Valluri Ramana Rao