Synopsys, Inc.

Virage Logic Corporation

Valery Vardanian

Yervant Zorian

Samvel Shoukourian

Gurgen Harutyunyan

Karen Amirkhanyan

Karen Aleksanyan

Hayk Grigoryan

Gevorg Torjyan

Alexander Shubat

Karen Darbinyan

Albert Harutyunyan

Tatevik Melkumyan

Aram Hakhumyan

Arman Davtyan

Sergey Karapetyan

An integrated circuit includes a memory and a memory test circuit, which when invoked to test the memory, is configured to generate one or more March tests applied to the memory. The memory test circuit is further configured to construct a table including a first index, a second index, and a first March test of the one or more March tests. The first index is associated with one or more families each characterized by a different length of the one or more March tests. The second index is associated with one or more mechanisms each characterized by a different property of the one or more March tests. The memory test circuit is further configured to generate a second March test from the first March test.

Testing electronic memories based on fault and test algorithm periodicity

A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.

Generation of memory structural model based on memory layout

A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.

Determining a desirable number of segments for a multi-segment single error correcting coding scheme

A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.

Detecting random telegraph noise induced failures in an electronic memory

A method and apparatus are described in which an optimal configuration of memory instances is determined. The optimal configuration of memory instances to be fabricated with built-in repair capacity and memory instances that are non-repairable may provide a maximum number of good chip dies per wafer. An amount of memory instances to be fabricated with built-in repair capacity as well as a remaining amount of memory instances to be fabricated without any built-in repair components in the integrated circuit design is determined relative to achieving the maximum number of good chip dies per wafer for a given defect density and wafer area. The amount of good dies produced per fabricated wafer for a populated amount of memories with built-in repair components is determined to be between an amount established by a minimum limit for the die area up to the amount established by a maximum limit for the die area.

Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer

A structural primitive verification tool for memory compilers is described. A first set of memory structural primitives are supplied by a designer by filling in fields of a presented user interface. The first set of structural primitives describe certain physical layout features of a proposed memory array in an integrated circuit. A first model of a memory instance derived from the first set of memory structural primitives supplied by the designer is compared to a second model of a memory instance derived from a memory layout file from a memory compiler under-test. The first model is verified against the second model to verify to an integrity of the first set of memory structural primitives supplied by the designer compared to the memory layout file derived from a second set of memory structural primitives configuring that memory instance from the memory compiler.

Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilers

A computer-implemented method for creating an integrated circuit, IC, test engine for testing a proposed IC memory array using new memory structural model. An IC designer inputs the number of words that can be stored and a column multiplexer ratio in a proposed IC memory array. A selection of one or more procedures is made from a library of computer-readable procedures. Each of the procedures is to produce one or more structural primitives that describe certain physical layout features of the proposed IC memory array, without analyzing a CAD layout file of the proposed IC memory array. The library of procedures as a whole translates between a physical model of a family of IC memory arrays and a user interface model of the family. A data background, DB, pattern is produced to be used by the test engine in testing the proposed IC memory array. This is done by executing the selected one or more procedures, wherein these procedures take as input the received number of words and column multiplexer size. Other embodiments are also described.

Memory modeling using an intermediate level structural description

In general, various methods, apparatuses, and systems are described in which logic executes, in series, a plurality of repair algorithms to generate a repair signature for a memory. The memory has a full set of redundant components associated with the memory. At least one or more of the repair algorithms employ a subset of redundant components that contains less than all of the redundant components in the full set when attempting to generate the repair signature.

Growing community of inventors

Yerevan, Armenia

Valery Vardanian