Winbond Electronics Corporation

Valery Teper

Nir Tasher

Uri Kaluzhny

Ziv Hershman

Moshe Alon

Tsachi Weiser

Dennis Chin Cheng

Ohad Falik

Koying Huang

Ilan Margalit

Leonid Azriel

Boaz Tabachnik

An electronic circuit with protection against eavesdropping by power analysis is provided. The electronic circuit includes: a storage element for storing a set of bits; a logic unit for processing the stored set of bits and providing a next state set of bits after two or more cycles, wherein in a first cycle, some of the stored set of bits are provided to the logic unit correctly and some are replaced by random values and in a last cycle, all of the stored set of bits are provided to the logic unit correctly; and a random bit generator that generates a random bit for each bit of the stored set of bits to determine which bits of the stored set of bits are to be provided correctly and which bits are to be replaced in each cycle.

Method of protecting electronic circuit against eavesdropping by power analysis and electronic circuit using the same

A system, comprising a logic circuit and delay circuitry, is described. The logic circuit is configured to perform a plurality of instances of a particular computation that is based on a plurality of inputs. The delay circuitry is configured to vary a power-consumption profile of the logic circuit over the plurality of instances, by applying, to the inputs, respective delays that vary over the instances, at least some of the delays varying independently from each other. Other embodiments are also described.

Protection from side-channel attacks by varying clock delays

An electronic circuit with protection against eavesdropping, including a first circuit element embedded in the electronic circuit, a second circuit element embedded in the electronic circuit, one or more connection lines between the first circuit element and the second circuit element, a first monitoring unit in the first circuit element for measuring capacitance of at least one of the connection lines between the first circuit element and the second circuit element, wherein the first monitoring unit is configured to identify changes in capacitance of the connection lines and to initiate actions to prevent eavesdropping in response to identifying changes.

Snooping detection between silicon elements in a circuit

An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits.

Protection of memory interface

A computing device includes an input bridge, an output bridge, a processing core, and authentication logic. The input bridge is coupled to receive a sequence of data items for use by the device in execution of a program. The processing core is coupled to receive the data items from the input bridge and execute the program so as to cause the output bridge to output a signal in response to a given data item in the sequence, and the authentication logic is coupled to receive and authenticate the data items while the processing core executes the program, and to inhibit output of the signal by the output bridge until the given data item has been authenticated.

Secured computing system with asynchronous authentication

There is provided a computerized mechanism for vulnerability evaluation in a layout having circuitry units as interceptors, comprising receiving a layout with interceptors incorporated therein at prearranged positions, virtually inducing faults in the layout by modeling a physical phenomenon that affects timings in the layout, detecting timing violations in the layout responsive to the induced faults based on discrepancies between the timings and provided specifications thereof determining vulnerability of the layout to faults according to detected faults, and wherein the method is performed on an at least one computerized apparatus configured to perform the method.

Level faults interception in integrated circuits

A monolithic integrated circuit device may include a supply voltage glitch detector for detecting improper supply voltage conditions. Advantageously, the detection threshold of the supply voltage glitch detector is adaptively set based on the mode of operation of the device or a particular part of the device, which is internally known to the device based on certain inputs received by the device, such as commands, interrupts, control signals, and so forth.

Method and apparatus for supply voltage glitch detection in a monolithic integrated circuit device

A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.

Memory device with secure test mode

Protecting memory interface

An Integrated Circuit (IC) includes signal distribution circuitry and protection circuitry. The signal distribution circuitry is configured to distribute a high-fanout signal across the IC. The protection circuitry includes a plurality of logic stages and detection circuitry. The logic stages are configured to receive multiple instances of the signal that are sampled at multiple sampling points in the signal distribution circuitry. The logic stages are interconnected to drive one another in accordance with a given topology so as to propagate abnormalities indicative of faults occurring in the signal distribution circuitry. The detection circuitry is configured to detect a fault in the signal distribution circuitry in response to an abnormality propagating in the plurality of logic stages.

Fault protection for high-fanout signal distribution circuitry

A non-volatile memory (NVM) device includes an NVM array, which is configured to store data, and control logic. The control logic is configured to receive data values for storage in the NVM array, and to write at least some of the received data values to the NVM array and simultaneously to write complements of the at least some of the received data values.

Protection against side-channel attacks on non-volatile memory

An apparatus for detecting tampering with a clock of a state-machine, comprising, a master state-machine having master states and driven by a master clock, the master states being switchable responsive to events, and an auxiliary state-machine having auxiliary states and driven by an auxiliary clock synchronous with the master clock, the auxiliary states being switchable responsive to a signal generated based at least on said events, consequently establishing a correspondence between the master states and the auxiliary states, thus ensuing that subsequent to tampering with the master clock the correspondence between the master states and the auxiliary states become discordant, thereby indicating that the master clock has been tampered with.

State-machine clock tampering detection

One or more lock words in a non-volatile memory with write ability correspond to lockable features of a protected system including the memory. A lockable feature should be locked when the corresponding lock word has a value equal to one of a limited number of predetermined locking combination(s). The locking combination(s) are selected so as to minimize the probability of the lock word waking up from manufacture with a value equal to one of the locking combination(s). In order to detect whether allowable usage of a lockable feature should be at a predetermined locked or unlocked level, multi-sampling of the corresponding lock word value is performed. If there is variation among the sampled values of the lock word, a malicious attack is identified. In one preferred embodiment, the multi-sampling occurs upon power up reset of the protected system and if a malicious attack is identified, the protected system is kept in reset.

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Petach Tikva, Israel

Valery Teper