Meta Platforms Technologies, LLC

Facebook Technologies, LLC

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Drew Eric Wingard

Alok Kumar Mathur

Sridhar Gurumurthy Isukapalli Sharma

Ennio Salemi

This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.

Artificial reality system having multi-bank, multi-port distributed shared memory

The disclosure is directed to techniques for dynamically managing memory in mixed mode cache and shared memory systems. For example, a system on a chip (SoC) comprises: a plurality of memories, including a first memory and a second memory, where each of the memories includes one or more cache lines; a first subsystem comprising a first compute element and the first memory; a second subsystem comprising a second compute element and the second memory; and a memory control unit of the SoC comprising processing circuitry and configured to: configure a shared memory with one or more cache lines of at least one of the plurality of memories; and flush, based on one or more tag control bits for the one or more cache lines of the shared memory, data from the shared memory to a backend storage separate from the SoC.

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