Stmicroelectronics S.r.l.

Stmicroelectronics International N.v.

Stmicroelectron S.r.l.

Valeria Bottarel

Sandro Rossi

Giulio Ricotti

Alessandro Nicolosi

Stefano Corona

Juri Giovannone

Fabio Quaglia

Niccolo′ Brambilla

Liliana Arcidiacono

Marco Terenzi

Silvia Marabelli

Niccolo' Brambilla

Fulvio Ottavio Lissoni

Alessandro Saccà

Niccolò Brambilla

In accordance with an embodiment, a method for controlling a constant on-time switched mode power converter includes: generating a pulse signal having an on-time; during a soft-start phase of the power converter, successively increasing the on-time from an initial duration to a final duration, wherein the final duration is larger than the initial duration; sensing an output voltage of the power converter and generating a feedback signal proportional to the output voltage; adjusting a frequency of the pulse signal based on the feedback signal and a reference signal; and driving a power switch with the pulse signal to control the power switch and regulate the output voltage.

Constant on-time power converter with adjustable pulse duration and soft-start control

An integrated circuit device includes: one or more switches of a Buck converter; and a control circuit for the Buck converter, including: a comparator configured to compare a feedback voltage of the Buck converter with a compensation ramp voltage; a pulse generator configured to generate, in response to a rising edge in a comparator output signal, a pulse signal for controlling the Buck converter; a transconductance amplifier (TA) configured to generate, at an output terminal of the TA, a current proportional to a difference between a reference voltage and the feedback voltage; a capacitor coupled between an output terminal of the TA and a reference voltage node; and a ramp signal generator configured to generate the compensation ramp voltage by adding a voltage at the output terminal of the TA and a ramp voltage having a gradient proportional to a switching frequency of the Buck converter.

Closed loop stability ramp implementation for Constant On-Time buck converter

In an embodiment, a switching converter includes: a switching stage configured to receive a direct current input voltage, receive a driving signal for driving the switching stage, and provide a direct current output voltage according to the input voltage and the driving signal; a driving stage configured to provide the driving signal to the switching stage; a current sensing circuit configure to sense an output current provided by the switching stage; and a voltage generation circuit configured to generate at least one supply voltage for powering the driving stage, and adjust the at least one supply voltage according to the output current.

Adjustable drive switching converter

In an embodiment, a switching converter includes: a switching stage including first and second switching devices for receiving an input voltage and for providing an output voltage; a driving stage including first and second driving devices for driving the first and second switching devices, respectively; a current sensing arrangement for sensing an output current provided by the switching stage; a voltage generation arrangement configured to generate a supply voltage for powering the driving stage, the voltage generation arrangement being configured to adjust the supply voltage according to the sensed output current; and a charge recovery stage configured to store a first electric charge being lost from the first driving device during driving of the first switching device and to release at least partially the stored first electric charge to the second driving device during driving of the second switching device.

DC-DC switching converter with adjustable driving voltages

A DC-DC switching converter includes power switches selectively coupling an output terminal with a first voltage or with a second voltage. A driver stage is coupled with the power switches for driving the power switches. A driver control stage is coupled with the driver stage for controlling the operation of the driver stage. An output current sensing circuit is coupled with the output terminal and with the driver control stage, and is configured to sense a sign of an output current delivered by the DC-DC switching converter at the output terminal and to generate control signals for the driver control stage. The driver control stage controls the operation of the driver stage according to states of the control signals received from the output current sensing circuit, for selectively delaying the activation of the power switches depending on the sensed sign of the output current.

Driver circuit for switching converters

In an embodiment a DC-DC switching power converter includes a switching circuitry including switches, the switching circuitry configured to receive a DC input voltage and generate a DC output voltage via switching the switches, a switching control circuitry configured to control switching of the switches with a switching signal having a corresponding switching frequency with a corresponding duty cycle, the DC output voltage generated by the switching circuitry depending on the duty cycle, wherein the switching control circuitry is configured to set the duty cycle based on a difference between the DC output voltage and a reference voltage in a closed loop configuration and a compensation network configured to provide stability to an operation of the DC-DC switching power converter, wherein the compensation network has a capacitance having a value depending on the switching frequency.

Adaptive compensation sytem for switching power converters

A direct current (DC) to DC (DC-DC) converter includes a comparator configured to set a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL configured increase the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer configured to selectively output a delayed version of the signal pulse; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit configured to adaptively adjust a precision of the DC-DC converter in accordance with a duty cycle of the DC-DC converter and a setpoint of the DC-DC converter.

Methods and apparatus for adaptively controlling direct current-direct current converter precision

A direct current (DC) to DC (DC-DC) converter includes a comparator setting a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL adjusting the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer selectively outputting a delayed version of the signal pulse; a phase detector operatively coupled to a system clock and the multiplexer, the phase detector generating a phase error between an output of the multiplexer and the system clock; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit adjusting the delay introduced to the signal pulse in accordance with the phase error.

Methods and apparatus for a direct current-direct current converter compatible with wide range system clock frequency

A circuit receives an input signal having a first level and a second level. A logic circuit includes a finite state machine circuit, an edge detector circuit, and a timer circuit. The finite state machine circuit is configured to set a mode of operation of the circuit. The edge detector circuit is configured to detect a transition between the first and second level. The timer circuit is configured to determine whether the first or second level is maintained over an interval, which starts from a transition detected by the edge detector circuit. The finite state machine circuit is configured to change the mode of operation based on the timer circuit determining that the first or second level has been maintained over the interval.

Control circuit and corresponding method

Switching circuitry includes first and second transistors in series between two terminals and including a common control node with a capacitance between the common control node and an intermediate point. A control circuit includes first and second circuits configured to charge and discharge the capacitance as a function of first and second control signals. The control circuit includes a third circuit having a plurality of diodes and a switch that operates when the voltage at the capacitance is greater than a threshold two diodes in cascade between the intermediate point and the common control node to enable current flow from the intermediate point to the common control node. When the voltage at the capacitance is smaller than the given threshold two diodes are connected in series between the common control node and the intermediate point to enable current flow from the common control node to the intermediate point.

Switching circuitry, related method and integrated circuit

A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.

Gate driver circuit for a half bridge or full bridge output driver stage and corresponding method for driving a half bridge or full bridge output driver stage

An energy-harvesting system includes a transducer to convert environmental energy into a harvesting electrical signal. A storage element stores electrical energy derived from conversion of the harvested environmental energy. A harvesting interface supplies an electrical charging signal to the storage element. The harvesting interface is selectively connected to the storage element in response to a control signal. The control signal causes the connection when the harvesting electrical signal exceeds a threshold. Conversely, the control signal causes the disconnection when the harvesting electrical signal is less than the threshold.

Energy harvesting system with selectively activatable harvesting interface, and method of energy harvesting

The operation of a circuit exhibiting a delay that is subject to a time spread as a function of process, voltage, and temperature variations is synchronized with a synchronization signal. A digital delay corresponding to the time spread is applied to the synchronization signal. The digital delay is generated via cascaded delay elements having respective delay values and by controlling the number of cascaded delay elements in the circuit that are applied to the synchronization signal.

Synchronization method, and corresponding device and integrated circuit

A differentiator generates a time derivative signal from a time-variable signal. A transconductance amplifier generates a biasing control signal as a function of the time derivative signal. A supply network functions to supply the differentiator and transconductance amplifier. The supply network is driven by the biasing control signal output from the transconductance amplifier. With this configuration, speed of operation of the differentiator and transconductance amplifier vary with the supply provided by the supply network, and the supply is modulated as a function of the received time-variable signal.

Circuit and method for adjusting the electric power supply of an energy-scavenging system

A low voltage isolation circuit is coupled between an input terminal for receiving a high voltage signal and an output terminal for transmitting the high voltage signal to a load. The isolation circuit includes a driving block; having a first driving transistor coupled between a first voltage reference and an intermediate node and a second driving transistor coupled between the intermediate node and a second voltage reference; an isolation block connected between the input and output terminals and, through a protection block to the intermediate node. The protection block includes first and second protection transistors (MD, coupled in anti-series to each other and having control terminals receiving complementary protection driving signals. The isolation block includes a voltage limiter block, a diode block and a control transistor connected across the diode block between the input and output terminals and having a control terminal connected to the intermediate node through the protection block.

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Novara, Italy

Valeria Bottarel