International Business Machines Corporation

Globalfoundries Inc.

Microsoft Technology Licensing, LLC

Intel Corporation

Valentina Salapura

Michael K Gschwind

Chung-Lung K Shum

Maged M Michael

Min Li

Ruchi Mahindru

Fadi Y Busaba

Eric M Schwarz

John Alan Bivens

Timothy John Slegel

Eugen Schenfeld

Harold Wade Cain, Iii

Clifford A Pickover

Alan G Gara

Harigovind Venkatraj Ramasamy

Minkyong Kim

Yaoping Ruan

Matthias Augustin Blumrich

Dan F Greiner

Maja Vukovic

Dong Chen

Philip Heidelberger

Martin Ohmacht

Robert William Wisniewski

Mark Edwin Giampapa

Jonathan D Bradbury

James R Kozloski

Christos J Georgiou

Brian Paul Gaucher

John Kevin O'Brien

Jonathan Lenchner

Burkhard Steinmacher-Burow

Pavlos Michael Vranas

Dirk Hoenicke

Ashish Kundu

Kathryn Mary O'Brien

Richard Edwin Harper

Paul William Coteus

Todd Edward Takken

Mahesh Viswanathan

Jonathan Hudson Connell, Ii

Robert G Farrell

George L Chiu

Krishnan Sugavanam

Alexandre E Eichenberger

David Osmond Melville

Ajay Mohindra

John A Gunnels

Shawn Anthony Hall

Amos Cahan

Zehra Noman Sura

Sameer Kumar

Gerard Vincent Kopcsay

Aaron K Baughman

Christian Jacobi

Michael A Blocksome

Joseph D Ratterman

Adam James Muff

Joseph N Kozhaya

Jinho Hwang

Bruce Martin Fleischer

Thomas M Gooding

Brett Olsson

Jeffrey Owen Kephart

Mark Gregory Megerian

Sameh W Asaad

Anup Kalia

Thomas Winters Fox

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Seetharami R Seelam

Charles David Wait

Thomas R Puzak

Michael Peter Perrone

Long Wang

James Anthony Marcella

Todd Alan Inglett

Sarbajit Kumar Rakshit

Li Feng Zhang

Michael S Gordon

Brian E Smith

Eric Vance Kline

Komminist S Weldemariam

Rogerio Schmidt Feris

Ashish Jagmohan

Michele M Franceschini

Anca Sailer

Richard Harold Boivie

Liana Liyow Fong

Thomas Mario Cipolla

Ying Li

Jim Alain Laredo

Anthony Cappa Spielberg

Evelyn Duesterwald

David Michael Daly

Jian Tan

Roxana Monge Nunez

John Martin Prager

Yandong Wang

A method for guiding an emergency vehicle to an emergency site includes receiving an emergency dispatch message including a location of an emergency. Present location information is received for an emergency vehicle. A route between the received present location and the received location of the emergency is calculated using area map data. Navigation guidance is provided to the emergency vehicle based on the calculated route. The calculated route and the present location information for the emergency vehicle are transmitted to an unmanned aerial vehicle (UAV). The UAV is automatically piloted ahead of the emergency vehicle, along the calculated route, using the calculated route and present location transmitted thereto. A traffic alert is transmitted from the UAV to influence traffic flow ahead of the emergency vehicle.

Method for guiding an emergency vehicle using an unmanned aerial vehicle

A method of organizing computer resources includes receiving a specification defining a plurality of quiescence groups of independent component instances for each of at least two services, and performing a first load balancing of the quiescence groups across a plurality of physical servers to define a plurality of supergroups while assigning each of the physical servers across the supergroups.

Hardware placement and maintenance scheduling in high availability systems

Embodiments are provided herein for efficient component communication and resource optimization in a disaggregated computing system. A first set of computing elements are used as in line accelerators and a second set of the computing elements are used as block accelerators within the disaggregated computing system. A switching operation is dynamically performed between the first set of computing elements and the second set of computing elements to perform a workload by rewiring one of a plurality of links associated with respective ones of the first set of computing elements and the second set of computing elements.

Efficient component communication through accelerator switching in disaggregated datacenters

A system, method, and computer program product for verifying signatures. The system includes at least one processing component, at least one memory component, and a reference storage comprising a set of reference signatures. The system also includes a model generator configured to generate a signature model based on the set of reference signatures. Further, the system includes a verification component configured to receive a signature, and determine whether the signature is valid.

Multifactor handwritten signature verification

A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.

Memory access request for a memory protocol

Portions of configuration state registers in-memory. An instruction is obtained, and a determination is made that the instruction accesses a configuration state register. A portion of the configuration state register is in-memory and another portion of the configuration state register is in-processor. Processing associated with the configuration state register is performed. The performing processing is based on a type of access and whether the portion or the other portion is being accessed.

Portions of configuration state registers in-memory

Various embodiments for optimizing memory bandwidth in a disaggregated computing system, by a processor device, are provided. Respective memory devices are assigned to respective processor devices in the disaggregated computing system, the disaggregated computing system having at least a pool of the memory devices and a pool of the processor devices. An analytic function is performed on data resident in the pool of the memory devices using memory bandwidth not currently committed to a primary compute task.

Opportunistic data analytics using memory bandwidth in disaggregated computing systems

Aspects of branch prediction are suppressed for branch instructions executing in a transaction, of a transactional memory environment, that is a re-execution of a previously aborted transaction.

Suppressing branch prediction updates until forward progress is made in execution of a previously aborted transaction

Embodiments for optimizing dynamic resource allocations for storage-dependent workloads in a disaggregated computing environment. A new workload is assigned to a subset of a plurality of processors, the subset of processors assigned a subset of a plurality of memory devices associated with a plurality of storage devices. A determination is made that the new workload is categorized as a storage-dependent workload having a storage need which can be met primarily by a subset of the storage devices after having identified whether data requests associated with the new workload can be satisfied by the subset of memory devices. Pursuant to determining the new workload is the storage-dependent workload, a storage related action is proactively performed to increase efficiency of the new workload prior to commencement of a performance of the new workload.

Optimizing dynamic resource allocations for storage-dependent workloads in disaggregated data centers

A value to be used in register-indirect branching is predicted and concurrently stored in a selected location accessible to one or more instructions. The value may be a target address used by an indirect branch and the selected location may be a hardware register, providing concurrent prediction of branch addresses and the update of register contents.

Concurrent prediction of branch addresses and update of register contents

A determination is made that a unit of memory that provides storage for one or more in-memory configuration state registers is to be pinned in a system that includes a guest operating system and one or more hosts at one or more host levels. Based on determining that the unit of memory is to be pinned, at least one host of the one or more hosts is notified that the unit of memory is to be pinned.

Automatic pinning of units of memory

Respective memory devices are assigned to respective processor devices in a disaggregated computing system, the disaggregated computing system having at least a pool of the memory devices and a pool of the processor devices. An iterative learning algorithm is used to define data boundaries of a dataset for performing an analytic function on the dataset simultaneous to a primary compute task, unrelated to the analytic function, being performed on the dataset in the pool of memory devices using memory bandwidth not currently committed to the primary compute task, thereby efficiently employing the unused memory bandwidth to prevent underutilization of the pool of memory devices.

Server resources in a data center are disaggregated into shared server resource pools, including an accelerator (e.g., FPGA) pool. Servers are constructed dynamically, on-demand and based on workload requirements, by allocating from these resource pools. According to this disclosure, accelerator utilization in the data center is managed proactively by assigning accelerators to workloads in a fine granularity and agile way, and de-provisioning them when no longer needed. In this manner, the approach is especially advantageous to automatically provision accelerators for data analytic workloads. The approach thus provides for a 'micro-service' enabling data analytic workloads to automatically and transparently use FPGA resources without providing (e.g., to the data center customer) the underlying provisioning details. Preferably, the approach dynamically determines the number and the type of FPGAs to use, and then during runtime auto-scales the FPGAs based on workload.

Utilizing accelerators to accelerate data analytic workloads in disaggregated systems

An instruction stream includes a transactional code region. The transactional code region includes a latent modification instruction (LMI), a next sequential instruction (NSI) following the LMI, and a set of target instructions following the NSI in program order. Each target instruction has an associated function, and the LMI at least partially specifies a substitute function for the associated function. A processor executes the LMI, the NSI, and at least one of the target instructions, employing the substitute function at least partially specified by the LMI. The LMI, the NSI, and the target instructions may be executed by the processor in sequential program order or out of order.

Latent modification instruction for substituting functionality of instructions during transactional execution

Embodiments for replicating data in a disaggregated computing system. A memory pool is allocated, where the memory pool includes allocated memory elements at a first site and allocated memory elements at a second site. The allocated memory elements are mapped at the first site to the allocated memory elements at the second site. A replication operation is initiated to mirror data stored within the allocated memory elements at the first site to the allocated memory elements at the second site. The allocated memory elements at the first site are directly connected through an independent networking connection to the allocated memory elements at the second site such that the replication operation is processed exclusively through compute resources at the first site.

Replicating workload and state data for disaster recovery in disaggregated datacenters

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Chappaqua, NY, United States of America

Valentina Salapura