Alcatel

Val Teodorescu

Serge Francois Fourcand

William L Long

Richard G Van Tyne, Jr

Jose Salmones

Curt McKinley

Donald Loewen

William L Brazell

Johnny Wheat

An alarm collection and routing method using a multi-stage clock distribution scheme in a signaling server organized into a plurality of uniquely addressable shelves. The signaling server includes a system timing generator, one or more clock distribution modules arranged in a nested hierarchical manner, and a plurality of bus control modules, wherein each bus control module interfaces with at least a portion of line cards disposed in a shelf. The system timing generator provides a framed serial control signal, SFI, for controlling the operation of the multi-stage clock distribution scheme, which encodes the IDs of the clock distribution modules and bus control modules. Each bus control module generates a Status signal, encoding it with alarm data and line card status information. The Status signals from the bus control modules are received by the clock distribution modules connected thereto and are multiplexed into a serial TDM bitstream (EAS signal) by each clock distribution module based on its ID. Multiplexed EAS signals are successively provided to higher levels of clock distribution modules, if any, in the nested hierarchy, each of which multiplexes the received EAS signals into a TDM bitstream having an aggregation of lower level alarm/status data as well as alarms produced at that level. The TDM EAS signal is ultimately provided to the system timing generator for appropriate action under the control of a suitable computing element.

Method and apparatus for routing alarms in a signaling server

A bus control module as a terminal stage for a multi-stage clock/alarm distribution scheme in a signaling server organized into addressable shelves. A system timing generator provides a framed serial control signal, SFI, addressing hierarchically arranged clock distribution modules and the bus control modules, to distribute a system clock to the bus control modules. Each bus control module provides a copy of the system clock to line cards with which it interfaces. The bus control module reports alarms and status signals from its line interface cards to the system timing generator using another framed serial signal. The bus control module forwards upstream towards the system timing generator a clock signal selected from clocks signals recovered by its line interface cards from received network signals.

Bus control module for a multi-stage clock distribution scheme in a signaling server

Matrix recovery and link maintenance for a signaling node in an SS7 network. The signaling node comprises a planar redundant switching matrix with master and standby sides. End devices for trunk interfacing and channel data control receive data and timing from the master side, de-coupled from data and timing paths of the standby side. In steady-state, revenue traffic between the SS7 network and the signaling node runs on the master side in a pulse code modulated (PCM) form. Test channels are set up on both sides. Test patterns are propagated on the test channels for monitoring failures of timing path, PCM data, and device communication. When a failure condition is detected on the master side, the signaling node transmits idle signaling to the network, so that the revenue traffic is suspended and the link is maintained in an in-service state.

Matrix recovery system and method in a telecommunications node

A multi-stage clock distribution scheme for use in a signaling server organized into a plurality of uniquely addressable shelves. The signaling server includes a system timing generator, one or more clock distribution modules arranged in a nested hierarchical manner, and a plurality of bus control modules, wherein each bus control module interfaces with at least a portion of line cards disposed in a shelf. The system timing generator provides a framed serial control signal, SFI, for controlling the operation of the multi-stage clock distribution scheme. The SFI signal encodes the IDs of the clock distribution modules and bus control modules whereby a system clock generated by the system timing generator based on a select reference input is successively fanned-out by the intermediate clock distribution modules based on address and ID information encoded in select fields of the SFI frames until the fanned-out system clocks are received by the bus control modules. Thereafter, each bus control module provides a copy of the system clock to the line cards controlled by it based on the SFI signal.

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Plano, TX, United States of America

Val Teodorescu