Agency for Science, Technology and Research

Infineon Technologies Ag

Institute of Microelectronics

Vaidyanathan Kripesh

Ranganathan Nagarajan

Ganesh Vetrivel Periasamy

Mahadevan Krishna Iyer

Mihai Dragos Rotaru

Seung Uk Yoon

Yu Jau Chen

Seung Wook Yoon

Holger Huebner

Tai Chong Chai

Holger Hübner

Xiaowu Zhang

Wai Kwan Wong

Chirayarikathuveedu Sankarapillai Premachandran

Damaruganath Pinjala

Navas Khan Oratti Kalandar

Chee Houe Khong

Hengyun Zhang

According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first support structure, a plurality of chips formed on the first support structure and a reinforcing structure formed on the first support structure, the reinforcing structure including an outer surrounding element which surrounds the plurality of chips and extends from a surface of the first support structure to a height higher than each of the plurality of chips. A method of manufacturing a semiconductor structure is also provided.

Semiconductor structure and a method of manufacturing a semiconductor structure

A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

RF and MMIC stackable micro-modules

A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least one first conductive layer is formed on the at least one first separation layer and is coupled to the bondpads. The at least one second conductive layer is formed on the at last one second separation layer wherein the at least one second conductive layer is electrically coupled to the at least one first conductive layer. The at least one third separation layer allows solder to be attached to the at least one second conductive layer for electrically coupling the solder to the bondpads. A chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.

Wafer level packages and methods of fabrication

A process for packaging semiconductor devices for flip chip and wire bond applications, wherein specific materials of the semiconductor devices are protected during device processing sequences and dicing procedures, has been developed. After definition of copper interconnect structures surrounded by a low k insulator layer, a protective, first photosensitive polymer layer comprised with a low dielectric constant is applied. After definition of openings in the first photosensitive polymer layer exposing portions of the top surface of the copper interconnect structures, a dicing lane opening is defined in materials located between copper interconnect structures. Conductive redistribution shapes are formed on the copper interconnect structures exposed in the openings in the first photosensitive polymer layer, followed by application of a protective, second photosensitive polymer layer. An opening is defined in the second photosensitive polymer layer exposing a portion of the top surface of a redistribution shape followed by placement of a solder ball in this opening. A reflow anneal procedure results in the solder ball wetting and overlying only the portion of the redistribution shape exposed in the opening in the second photosensitive polymer layer. Separation of the solder ball, flip chip regions from the non-solder ball, wire bond regions is accomplished via a dicing procedure performed in the dicing lane.

Polymer encapsulated dicing lane (PEDL) technology for Cu/low/ultra-low k devices

In an improved method for bumped wafer thinning, a wafer is provided having a front side and a back side wherein contact pads are formed on the top surface. A dry film is formed on the front side of the wafer and openings are provided in the dry film to the contact pads. Interconnections, such as solder bumps, are formed within the openings on the contact pads. A back grind tape or carrier is attached to the dry film and overlying the interconnections. Thereafter, the wafer is thinned from the back side of the wafer.

Method for ultra thinning bumped wafers for flip chip

A soldering agent for use in diffusion soldering processes contains, in a soldering paste, a mixture of at least partially metallic grains of a high-melting metal and a solder metal. In a diffusion soldering process, the solder metal reacts completely with the high-melting metal and metals belonging to parts that are to be joined to one another by the soldering process, to form an intermetallic phase.

Soldering agent for use in diffusion soldering processes, and method for producing soldered joints using the soldering agent

A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing metal on one of two wafers; bonding the two wafers using the metal deposited on the one of the two wafers; forming a through-wafer via in one of the two wafers; filling the through-wafer via with a conductive material; and forming a cavity in the one of the two wafers having the through-wafer via wherein the cavity is superposable over a device.

Wafer-level package for micro-electro-mechanical systems

Inter-connectors are typically used for interconnecting electronic components. Interconnections between electronic components are generally classified into at least two broad categories of &ldquo;relatively permanent&rdquo; and &ldquo;readily demountable&rdquo;. A &ldquo;readily demountable&rdquo; connector includes a spring-like contact structure of one electronic component for connecting to a terminal of another electronic component. The spring-like contact structure, also known as an inter-connector, generally requires a certain amount of contact force to effect reliable pressure contact to a terminal of an electronic component. Therefore, the shape and metallurgy of the inter-connector are important factors in determining the effectiveness of the inter-connector for making pressure connection to a terminal of the electronic component. Conventional methods of making such an inter-connector use lithographic and planarisation methods to &ldquo;make&rdquo; the inter-connectors in segments. This results in the inter-connector segments having joints therebetween. Metallurgically, the joint stress due to joining a pair of inter-connector segments and stress concentration at the joints due forces applied to the inter-connector can lead to the mechanical failure of the inter-connector in Mathieu. An embodiment of the invention uses lithographic techniques and heat treatment methods for forming a structure channel defining the shape and dimension of an inter-connector. The structure channel is then used to &ldquo;mold&rdquo; a reproduction of the inter-connector having a single continuous physical segment.

Wafer-level inter-connector formation method

A solder metal made of a eutectic or stoichiometric composition including at least two metallic or semiconducting elements is applied to a contact (of the semiconductor component, brought into contact with the metal layer of a metallized film and alloyed by heating into the metal layer of the film, thereby producing an electrically conductive connection having a higher melting point. A solder metal that is particularly suitable for such a purpose is the Bi In (melting point 73&deg; C.), Bi Sn , or In Sn , or BiIn, or BiIn .

Method for contact-connecting a semiconductor component

Method and apparatus for fluid-based cooling of heat-generating devices are disclosed. A heat-generating device is mounted on a carrier. The heat-generating device is spatially displaced from the surface of the carrier, thereby forming a channel. The heat-generating device and the carrier are enclosed in an enclosure having an inlet and an outlet. A substantially electrically non-conductive cooling fluid for introduction into the enclosure and into the channel and expulsion from the enclosure and for extracting heat from and thereby cooling the heat-generating device and the carrier.

Growing community of inventors

Singapore, Singapore

Vaidyanathan Kripesh