Intel Corporation

Vaibhav Singh

Kuljit Singh Bains

Wei P Chen

Rajat Agarwal

Wei Wu

Theodros Yigzaw

Jing Ling

Deep K Buch

John G Holm

Andrew M Rudoff

Sreenivas Mandava

Kjersten E Criss

Hsing-Min Chen

A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)

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Hillsboro, OR, United States of America

Vaibhav Singh