Silicon Laboratories Inc.

University of California

Vaibhav Karkare

Aaron J Caffee

Brian G Drost

Dejan Markovic

Signal recording sensor systems in accordance with embodiments of the invention include sensors capable of sensing and capturing electrophysiological signals in the presence of interference signals, an analog front-end including circuitry configured to record electrophysiological input signals as a voltage, and an analog to digital converter including a voltage-controlled-oscillator configured to convert the recorded analog electrophysiological input signal to a phase output. While such signal recording sensor systems can be used in the recording of biosignals and/or electrophysiological signals generated from living organisms, signal recording sensor systems in accordance with embodiments of the invention are not limited to recording biosignals and/or electrophysiological signals.

Saturation-tolerant electrophysical recording interface

A low-noise voltage reference generator that utilizes internal gain and feedback to generate an output signal having reduced sensitivity to power supply variations and loading conditions is described. A method includes generating a current based on a voltage drop across a resistor. The voltage drop is based on a second voltage drop across a gate terminal of a transistor and a source terminal of the transistor. The method includes the current using a reference voltage to generate a mirrored current through a node coupled to the drain terminal of the transistor. The method includes generating a level-shifted voltage using a voltage on the node. The method includes buffering the level-shifted voltage using a power supply voltage to generate the reference voltage.

Low noise reference voltage generator and load regulator

A technique for reducing noise in an output clock signal of a feedback control system (e.g., a PLL or FLL) samples rising edge errors and falling edge errors between a reference clock signal and a feedback clock signal. The technique applies edge alignment correction to reduce or eliminate edge alignment errors between the reference clock signal and the feedback clock signal. A PLL generates an output clock signal based on a control signal generated using an error signal generated based on a rising edge difference between a rising edge of an input clock signal and a corresponding edge of an edge alignment corrected feedback clock signal and based on a falling edge difference between a falling edge of the input clock signal and a corresponding edge of the edge alignment corrected feedback clock signal. The edge alignment corrected feedback clock signal is partially based on the output clock signal.

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San Jose, CA, United States of America

Vaibhav Karkare