International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Marvell Asia Pte., Ltd.

Vaibhav A Ruparelia

Krishnan Santhana Rengarajan

Janakiraman Viraraghavan

Davinder Aggarwal

Neha Singh

Indranil Som

Michal Rakowski

Prateek Kumar Sharma

Panduga Shiva Shankar Reddy

Riddhi Nandi

Kuppireddy Vasudeva Reddy

Vasudeva Reddy KuppiReddy

Avijit Chatterjee

Embodiments of the disclosure provide a peak voltage detection circuit with reduced charge loss. A circuit structure of the disclosure includes a peak voltage detector having a first input node coupled to an input line and a second input node coupled to a first electrically actuated switch. The peak voltage detector coupling the first input node and the second input node to an output node, and a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor. The first electrically actuated switch couples the capacitor to the second input node of the peak voltage detector. The input line is coupled to a control node of the first electrically actuated switch and a control node of the second electrically actuated switch.

Peak voltage detection circuit with reduced charge loss

Disclosed is a thermal stabilization circuit including a heater, which is adjacent and thermally coupled to a closed-curve waveguide of an optical ring resonator, and an analog feedback circuit, which includes a fully autonomous analog feedback loop from a drop port of a bus waveguide of the optical ring resonator to the heater. This analog feedback circuit is configured to dynamically control the electrical power provided to the heater and, thereby to dynamically control the thermal output of the heater in order to tune the ring resonance wavelength to the operating laser wavelength. The analog feedback circuit is further configured to be independent of input power, to be power efficient, to have a relatively small footprint, to have a tunable time constant and to facilitate adjustable wavelength locking. Also disclosed is a device (e.g., a ring-based transceiver or the like), which includes multiple optical ring resonators and corresponding thermal stabilization circuits.

Thermal stabilization circuit for an optical ring resonator

A distributed arithmetic feed forward equalizer (DAFFE) and method. The DAFFE includes look-up tables (LUTs) in offset binary format. A DA LUT stores sum of partial products values and an adjustment LUT stores adjustment values. DA LUT addresses are formed from same-position bits from all but the most significant bits (MSBs) of a set of digital words of taps and an adjustment LUT address is formed using the MSBs. Sum of partial products values and an adjustment value are acquired from the DA LUT and the adjustment LUT using the DA LUT addresses and the adjustment LUT address, respectively. Reduced complexity downstream adder(s) (which result in reduced power consumption) compute a total sum of the sum of partial products values and the adjustment value (which compensates for using the offset binary format and dropping of the MSBs when forming the DA LUT addresses) to correctly solve a DA equation.

Feed forward equalizer with power-optimized distributed arithmetic architecture and method

Disclosed is a power-optimized distributed arithmetic (DA)-based feed forward equalizer (FFE) that performs on-demand equalization processing of a data sample. Specifically, a data stream is represented by digital words, which indicate signal levels at taps on a transmission medium. A screener applies formulas to selected taps as opposed to all taps (e.g., to the main cursor tap, which corresponds to the current data sample, and to specific pre-cursor and post-cursor taps, which correspond to immediately proceeding and following data samples) to determine whether the current data sample (which should indicate a specific two-bit symbol) has degraded during transmission to a point where equalization processing is required. If so, a bypass flag is set to a first level so that the data sample is subjected to equalization processing. If not, the bypass flag is set to a second level so that such processing is bypassed. Also disclosed is a corresponding method.

On-demand feed forward equalizer with distributed arithmetic architecture and method

A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle.

Generic design rule checking (DRC) test case extraction

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Bengaluru, India

Vaibhav A Ruparelia