Intergraph Corporation

Dell USA L P

Intergraph Hardware Technologies Company

Vahid Samiee

Arthur C McKinney

Charles H McCarver, Jr

Alan E Brown

Eduard F Boeckmann

Vern Brethour

A method for maintaining coherent data in a multiprocessor system having a plurality of processors coupled to main memory, where each processor has an internal cache which is externally unreadable outside the processor. The method includes requesting data associated with a memory location in main memory and determining if an external cache coupled to an application specific integrated circuit associated with a second processor contains a reference to the requested data. A snoop cycle is performed on the second processor if the external cache has a reference to the requested data, whereupon a determination is made as to whether the requested data has been modified.

Multi-processor data coherency

A high-availability parallel processing server has multiple processors that are grouped into processor clusters and a plurality of memory segments. Each cluster may have up to four processors, and there may be up to five clusters of processors. Each of the processor clusters has dedicated memory buses for communicating with each of the memory segments. The server may be designed to maintain coherent interaction between all processor clusters and the memory segments.

High-availability super server

By separating a power regulator at a point between the output inductor and the output capacitor of the regulator, the capacitive output section can be located close to a processor (or other load device) while the remaining portion of the regulator can be placed in another location away from the processor. With the capacitive output section located close to the processor and valuable system board space can be saved.

Sectionalized power regulator separated between an output inductor and

Transceivers for bus communications using GTL-type transmission-line bus structures provide improved clamping of an initially ON output pulse of a communication bus driver and adds an active pull-up function inside the integrated circuit that does not change the external circuit nor require additional functional external circuit corrections. Receivers may contain an active pull-up for added signal quality improvement Improved clamping and active pull-up allow reduced width of the channel of the N-channel CMOS output transistor. A drive/receive clamp may be added to a sequential pull-up circuit and an active pull-up circuit for better performance at higher frequencies. A related method may comprise first switching OFF an active pull down circuit and switching ON an active pull-up circuit, where the active pull-up circuit clamps the driver output voltage from falling below a first voltage. Then switching OFF a first clamping circuit, where the first clamping circuit clamps the driver output voltage from exceeding a second voltage when the first damping circuit is ON, and where the second voltage is greater than the first voltage. And then switching OFF a second clamping circuit, where the second clamping circuit clamps the driver output voltage from exceeding a third voltage when the second clamping circuit is ON, and where the third voltage is greater than the second voltage.

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Austin, TX, United States of America

Vahid Samiee