Ciena Corporation

Vahid M Naraghi

Xiaojin Liu

Bashar Abdullah

Daniel Lee

Kelly Donald Fromm

Systems, circuits, and methods for synchronizing devices in the time-domain are provided. A method, according to one implementation, includes determining a round-trip number based on a width of one cycle of a timestamping clock signal. The round-trip number is equal to a plurality of times that a clock signal is to be transmitted in a loop from a timing-leader component to a timing-follower component and back to the timing-leader component. The method also includes utilizing the timestamping clock signal to detect a cumulative time delay that results when the clock signal is transmitted in the loop a number of times equal to the round-trip number. The cumulative time delay is configured to enable synchronization of the timing-follower component with the timing-leader component.

Detecting time delay between circuits to achieve time synchronization

A node can include a clock; and mapper circuitry configured to determine a timestamp from the clock, and transmit the timestamp to a second node in a Radio over Ethernet (RoE) frame with the timestamp in a control subtype and with an operational code (opcode) that designates the timestamp is in the frame. The node can also include a demapper circuit configured to receive a second timestamp from the second node in a second RoE frame, and provide the second timestamp to a Differential Clock Recovery (DCR) circuit for adjustment of the clock to a second clock at the second node.

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San Jose, CA, United States of America

Vahid M Naraghi