Microsoft Technology Licensing, LLC

Vadym Kliuchnikov

Alexei V Bocharov

Michael Edward Beverland

Martin Henri Roetteler

Krysta Marie Svore

Guang Hao Low

Adam Edward Paetznick

Jon Yard

Kristin E Lauter

Alexander Vaschillo

Nicolas Guillaume Delfosse

Thomas Haener

Nathan O Wiebe

Zhenghan Wang

Christopher Granade

Xingshan Cui

Sebastian Schoennenbeck

Andres C Paz

Dmitry Vasilevsky

Eddie Schoute

A computing system including one or more processing devices configured to receive a stabilizer channel sequence of three or more stabilizer channels and respective fault sets. The one or more processing devices compute a lower-bound channel distance of the stabilizer channel sequence at least in part by computing lower-bound channel distances of compositions of adjacent pairs of stabilizer channels. For a stabilizer channel and a plurality of partition timestep counts, computing the lower-bound channel distance further includes receiving an indication of whether there exists a partition of the fault set of that stabilizer channel that has that partition timestep count and for which the stabilizer channel is time-local. Computing the lower-bound channel distance further includes selecting a lowest value among the lower-bound channel distances of the compositions and each of the partition timestep counts that has a time-locality-satisfying partition. The one or more processing devices output the lower-bound channel distance.

Lower-bounding distance of stabilizer channel sequence

A computing system including one or more processing devices configured to identify one or more severe hook faults in a stabilizer channel. Identifying the severe hook faults includes receiving a circuit channel check matrix, the columns of which indicate values of checks associated with elementary faults of the stabilizer channel. Identifying the severe hook faults further includes receiving a phenomenological channel check matrix as a sub-matrix of the circuit channel check matrix, receiving a logical effect matrix, and receiving a weight vector that indicates probability weights of the elementary faults. Based at least in part on the circuit channel check matrix, the logical effect matrix, the phenomenological channel check matrix, and the weight vector, identifying the severe hook faults further includes computing column indices of columns of the circuit channel check matrix that correspond to the severe hook faults. The processing devices output an indication of the severe hook faults.

Identifying severe hook faults of stabilizer channel

A computing system including a processor configured to receive a stabilizer circuit specification of a stabilizer circuit that includes one or more elementary operations. The elementary operations are each selected from the group consisting of an allocation of one or more qubits in a stabilizer state, an allocation of one or more random classical bits, a Clifford unitary, a Pauli unitary conditional on respective parities of measurement outcomes and/or respective parities of the random classical bits, a joint multi-qubit Pauli measurement, and a destructive one-qubit Pauli measurement. The processor is further configured to compute a standardized stabilizer instrument specification of a stabilizer instrument based at least in part on the stabilizer circuit specification. The standardized stabilizer instrument specification includes an input Clifford unitary, an output Clifford unitary, and a plurality of bit matrices. The processor is further configured to store the standardized stabilizer instrument specification in memory.

Stabilizer instrument specification for stabilizer circuit

A low-cost solution for performing a quantum operation provides for defining a target unitary that rotates a single qubit by a target rotation to place the qubit in a target state. The method further provides for identifying multiple projective rotation circuits that each implement an approximation of the target rotation upon successful measurement and assigning a selection probability to each of the multiple identified projective rotation circuits, the selection probability being defined by a metric that increases in value in proportion to a proximity between a qubit state resulting from the approximation and the target qubit state. The method further provides for probabilistically selecting one of the multiple projective rotation circuits according to the assigned selection probabilities and outputting a circuit definition that includes the selected projective rotation circuit.

Mixing techniques for probabilistic quantum circuits with fallback

A method for performing long-range multi-qubit measurements in a quantum circuit utilizes a graph that maps qubits of the quantum circuit to nodes that are connected to one another by edges. The method provides for identifying sets of the nodes on the graph corresponding to sets of qubits targeted by multi-qubit operations in a quantum algorithm and for defining a group of edge-disjoint paths connecting the nodes of each set. The group of edge-disjoint paths is defined such that no two of the paths in the group share an edge. The method further provides for performing a set of operations to entangle the qubits corresponding to the to the identified set of nodes that are included in each path in the group and for performing the set of multi-qubit operations on the entangled sets of the qubits.

Edge-disjoint paths for long-range multi-qubit operations in quantum circuit

A method to digitally simulate an evolving quantum state of a qubit register of a quantum computer is enacted in a computer system. The quantum state is represented as an array of complex-valued amplitudes, where each amplitude is associated with an individual qubit of the qubit register, and where the quantum state is separable as a product of the individual quantum states of each qubit. One or more quantum-program instructions corresponding to a quantum circuit are received, and the amplitudes of the array are adjusted to reflect a change in the quantum state pursuant to execution of the quantum circuit, the change preserving the separability of the quantum state as a product of individual quantum states of each qubit. One or more of the adjusted amplitudes are then outputted computationally, in such form as to be receivable as input to a computer program.

Separable-state simulation of quantum program code

The disclosed technology includes example embodiments that provide a framework for testing quantum programs in a manner similar to unit testing of classical programs by using a simulator that can predict the probability of measurements in a quantum system (known as a 'strong simulator'). For a particular quantum program, embodiments of the disclosed technology use information exposed by strong simulation that would not otherwise be available to compare the given program to a desired reference program.

Strong simulation methods for unit testing quantum software

Examples are disclosed relating to obtaining a solution to a multiproduct formula of order m to solve a quantum computing problem comprising a product formula. One example provides a method comprising selecting a set of exponents k, wherein each kis a real number and is an exponent in a linear combination of product formulas. Based on the set of exponents k, a set of pre-factors ais determined based on an underdetermined solution to an m&#xd7;M system of linear equations, where M is a number of lower-order product formulas in the linear combination of product formulas. The set of exponents kand the set of pre-factors aare used to solve the quantum computing problem comprising the product formula. By minimizing the set of exponents kand the set of pre-factors a, sparse solutions to the multiproduct formula are generated, reducing computational time and scaling.

Methods for obtaining solutions to multiproduct formulas

This application concerns methods, apparatus, and systems for performing quantum circuit synthesis and/or for implementing the synthesis results in a quantum computer system. In certain example embodiments: a universal gate set, a target unitary described by a target angle, and target precision is received (input); a corresponding quaternion approximation of the target unitary is determined; and a quantum circuit corresponding to the quaternion approximation is synthesized, the quantum circuit being over a single qubit gate set, the single qubit gate set being realizable by the given universal gate set for the target quantum computer architecture.

Method and system for approximate quantum circuit synthesis using quaternion algebra

Certain ensembles of metapletic anyons allow for topologically protected encoding and processing of quantum information. Such processing is done by sequences of gates (circuits) drawn from a certain basis of unitary metaplectic gates. A subject unitary operator required for the desired processing can be approximated to any desired precision by a circuit that has to be effectively and efficiently synthesized on a classical computer. Synthesis methods use unitary reflection operators that can be represented either exactly or by ancilla-assisted approximation over the basis of metaplectic gates based on cost-optimizing determinations made by the synthesis algorithm.

Efficient topological compilation for metaplectic anyon model

Efficient synthesis of arbitrary quantum states and unitaries from a universal fault tolerant gate-set (e.g., Clifford+T) is a goal in quantum computation. As physical quantum computers are fixed in size, all available qubits should be used if it minimizes overall gate counts, especially that of the expensive T-gates. In this application, a quantum algorithm is described for preparing any dimension-N quantum state specified by a list of N classical numbers, that realizes a trade-off between space and T-gates. Example embodiments exploit(&#x3bb;) ancilla qubits, to reduce the T-gate cost to Notably, this it proven to be optimal up to logarithmic factors for any &#x3bb;=o(&#x221a;{square root over (N)}) through an unconditional gate counting argument. Though(N) Clifford gates are always required, only(&#x221a;{square root over (N)}) T-gates are needed in the best case, which is a quadratic improvement over prior art. Similar statements are provien for unitary synthesis by reduction to state preparation.

Trading t-gates for qubits in arbitrary state and unitary synthesis

Quantum circuits are synthesized based on a projective gate set derived from a set of single-qubit gates, typically a basis set such as the Clifford+T gates or the V-gates. An initial projective gate set is used to determine at least one characteristic of a quaternion algebra, and the quaternion algebra is used to define a new projective gate set. Exactly synthesizable unitaries are identified, and a circuit approximating a target unitary is defined in the single-qubit gate set by mapping from the new projective gate set.

Method and system for quantum circuit synthesis using quaternion algebra

Methods for generating quantum computing circuits by distributing approximation errors in a quantum algorithm are described. A method includes decomposing a quantum algorithm into quantum circuits. The method includes using at least one processor, automatically performing a step-wise decomposition of the quantum algorithm until the quantum algorithm is fully decomposed into the quantum circuits, where the automatically performing the step-wise decomposition results in a set of approximation errors and a set of parameters to instantiate at least a subset of the quantum circuits corresponding to the quantum algorithm, such that an overall approximation error caused by the automatically performing the step-wise decomposition is maintained below a specified threshold approximation error.

Generating quantum computing circuits by distributing approximation errors in a quantum algorithm

Methods are provided for exact synthesis of unitaries for qudit and multi-qubit systems. In addition, state preparation methods are provided. The syntheses produce circuits that have lowest cost for a given cost function.

Exact quantum circuits and circuit syntheses for qudit and multiple qubit circuits

Methods for compiling single-qubit quantum gates into braid representations for non-Abelian quasiparticles described by the Fibonacci anyon model are based on a probabilistically polynomial algorithm that, given a single-qubit unitary gate and a desired target precision, outputs a braid pattern that approximates the unitary to desired precision and has a length that is asymptotically optimal (for a circuit with such property). Single-qubit unitaries that can be implemented exactly by a Fibonacci anyon braid pattern are classified, and associated braid patterns are obtained using an iterative procedure. Target unitary gates that are not exactly representable as braid patterns are first approximated to a desired precision by a unitary that is exactly representable, then a braid pattern associated with the latter is obtained.

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Redmond, WA, United States of America

Vadym Kliuchnikov