Motorola Corporation

Vadim Vayzer

Avraham Ganor

Avi Hagai

Avi Shalev

Stefania Gandal

Boris Zabarski

Eliyahy Shasha

A method and a device for translating a hierarchical address, the device is adapted to receive a destination address, to search an array of sorted binary string being associated with a group of addresses reachable through the device, and to provide a best matching address, the device comprising: a content addressable memory module, for storing a first portion of the array of sorted binary strings; a fast memory module, for storing a second portion of the sorted binary strings; a memory module, for storing a remaining portion of the tree of sorted strings; and a search engine, coupled to the content addressable memory unit module, the fast memory module and the memory module, configured to receive a destination address, access at least the fast memory unit and the memory unit and to find the best matching address.

Method and apparatus for performing hierarchical address translation

A communication system ( ) comprises interfaces ( ) at communication channels ( , respectively), coupled to a controller ( ) by an address bus ( ) and multiplexer ( ). The interfaces ( ) receive data cells and provide status signals (e.g., clav) indicating, for example, cell availability, independently from interface addresses (ADDR) being present at the address bus ( ). The interfaces ( ) continuously send the status signals to the multiplexer ( ) which receives the interface address (ADDR) at a control input ( ) and forwards the status information of the currently addressed interface to the controller ( ).

Communication system with physical interface and communication controller, and method

A communication system ( ) has a first processor ( ) and a second processor ( ). The first processor ( ) has a first number of address bits (e.g., A&equals;5) to select a first device ( ), and the second processor ( ) has a second number of address bits (e.g., B&equals;4 to select a second device ( ). The processors ( ) are coupled to the devices ( ) by a shared bus ( ) with a total number of bit lines ( ) which is smaller than or equal to the sum of the first and second numbers of bits (e.g., N&equals;8). The bit lines ( ) are assigned to a first outer set ( ), a second outer set ( ) and to an inner set ( ). LSB-bits from the first processor ( ) are coupled to the first outer set ( ), LSB-bits from the second processor ( ) are coupled to the second outer set ( ), and MSB-bit of first and second processors ( ) are multiplexed to the lines of the inner set ( ).

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Petach-Tikva, Israel

Vadim Vayzer