Impinj, Inc.

Inphi Corporation

Clariphy Communications, Inc.

Silicon Laboratories Inc.

Massachusetts Institute of Technology

Virage Logic Corporation

University of California

Vadim Gutnik

Oscar Ernesto Agazzi

Mario Rafael Hueda

Diego Ernesto Crivelli

Hugo Santiago Carrer

Norman L Swenson

Paul Voois

Ramiro Rogelio Lopez

Martin Ignacio Del Barco

Jorge Manuel Finochietto

Christopher J Diorio

John D Hyde

Todd E Humes

Damian Alfonso Morero

Alfredo Javier Taddei

Matias German Schnidrig

Mauro Marcelo Bruni

Federico Nicolas Paredes

Elvio Adrian Serrano

Martin Carlos Asinari

Facundo Abel Alcides Ramos

Alejandro Javier Schwoykoski

Pablo Gustavo Quiroga

Roman Antonio Arenas

Scott A Cooper

Adrián Ulises Morales

Geoffrey O Hatcher

Shih Cheng Wang

Jeffrey Zachan

Michael Yeo

Andre Chartrand

María Laura Ferster

Alberto Pesavento

Theron Stanford

Yanjun Ma

Anantha P Chandrakasan

William T Colleran

Morteza Azarmnia

William Vanscheik

Ronald A Oliver

Michael Henderson Perrott

Roger T Howe

Jerrell P Hein

Kurt Eugene Sundstrom

Clark Tu-Cuong Nguyen

Philip David Steiner

David D Dressler

Maria Laura Ferster

Ulises Morales

Laura Maria Ferster

A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Coherent transceiver architecture

A transceiver for fiber optic communications. The transceiver can include a transmitter module having a transmitter host interface configured to receive an input host signal; a transmitter framer configured to frame the input host signal and to generate a framed host signal; and a transmitter coder configured to encode the framed host signal to generate an encoded host signal for transmission over a communication channel. The transceiver can also include a receiver module having a bulk chromatic dispersion, fiber length estimation, and coarse carrier recovery circuit configured to equalize a digital input ingress signal to generate an equalized ingress signal; a receiver framer configured to frame the equalized ingress signal to generate a framed ingress signal; and a receiver host interface configured to output the framed ingress signal. The receiver host interface is compatible with a framing protocol of the receiver framer.

Single-chip transceiver with electronic dispersion compensation for coherent optical channels

A transceiver for fiber optic communications.

A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Apparatus and methods for digital-to-analog conversion are disclosed. In one embodiment, an electronic system includes a bias circuit and a digital-to-analog converter (DAC) including an input that receives a digital input signal and an output that drives a transmission line. The digital input signal can be used to control a magnitude and polarity of an output current of the DAC. The DAC further includes one or more p-type metal oxide semiconductor (PMOS) termination transistors that receive a first bias voltage from the bias circuit and one or more n-type metal oxide semiconductor (NMOS) termination transistors that receive a second bias voltage from the bias circuit. The bias circuit controls the voltage levels of the first and second bias voltages to control the termination transistors' small signal resistance to actively terminate the DAC's output.

Apparatus and methods for active termination of digital-to-analog converters

An RFID tag is configured to adjust its current clock frequency to conserve tag power while receiving a reader signal and/or backscattering a signal. The tag may determine whether to adjust its current clock frequency based on one or more timing parameters, which may be determined from a reader command and/or from a signal to be backscattered. The counting rate and/or limit of a tag counter and/or the power supplied to a tag component may also be adjusted. The current tag clock frequency may be adjusted during the signal reception/backscattering process and optionally restored once the process is completed.

RFID tag dynamically adjusting clock frequency

Apparatus and methods for actively terminated digital-to-analog conversion

A method of calibrating an oscillator within a Radio-Frequency Identification (RFID) tag includes storing a plurality of calibration values within a memory structure. Each of the calibration values corresponds to a respective oscillation frequency of the oscillator. A selected calibration value is selected from the plurality of calibration values stored, according to a first selection criterion. The oscillator is then calibrated in accordance with the selected calibration value.

Radio-frequency identification tag with oscillator calibration

RFID tags are configured to adjust their clock frequency in order to meet predefined limits for reply frequencies to conserve tag power. A deviation of computed tag reply frequency from a reader commanded reply frequency is used to determine an adjustment to the tag clock frequency. The tag clock frequency may be adjusted during backscatter and restored once backscattering is completed.

Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) of a Radio Frequency Identification (RFID) tag such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, and/or a complex logic circuit function.

RFID tag with redundant non-volatile memory cell

Growing community of inventors

Irvine, CA, United States of America

Vadim Gutnik