Magnetic Peripherals Inc.

Seagate Technology Incorporated

Vadim B Minuhin

Vladimir Kovner

Srinivasan Surendran

Vernon F VonDeylen

Steven V Holsinger

Bernardo Rub

Shafaollah Dahandeh

Evgeny J Berzon

Vernon F Von Deylen

Robert E Caddy, Jr

A second order filter-delay element for use in a generalized analog transversal equalizer is described which provides phase and group delay responses equivalent to low-pass filters of third and fourth order. In addition, the filter-delay element provides sufficient values of delays required for proper operations of the analog generalized transversal equalizer despite having a low order. In addition, a method of generating the lower order filter-delay element is described. Also, a circuit embodying an active C-transconductor realization of a second order filter-delay element for use in a generalized analog transversal equalizer with a transfer function designed as a result of performing the method is described.

Second order filter-delay element for generalized analog transversal equalizer

A magnetic recording readback channel having an equalizer and a self synchronizer is described. The equalizer equalizing an input signal to an approximation of selected waveform. The equalizer including an analog, continuous-time frequency-domain prefilter which generates a preconditioned signal from the input signal. The equalizer further including a sampler which derives discrete-time samples appropriate for sequential sampled data decoding from the preconditioned signal and a sampling clock. The self-synchronizer generating the sampling clock from differentiation of a readback signal by utilizing an analog continuous-time filtering channel which is different from the equalizer and configured in parallel to the equalizer. The self-synchronizer including a phase locked loop which generates the sampling clock from detected magnetic transitions on a magnetic medium and which corrects the sampling clock based upon moments of detected peak pulses in the readback signal. The self-synchronizer further including a timing delay circuit which delays the sampling clock by an optimal amount and calibrates the sampling clock to an optimal phase during a sector preamble readback.

Analog self-synchronization subsystem based on peak detection and post processing in a sampled channel of digital magnetic recording

Improved self-synchronization in a sampled magnetic recording channel employing time-domain equalization. The channel includes a time-domain equalizer which filters an input, readback signal to an approximation of a selected target waveform. The equalizer includes a plurality of serially connected analog filter sections having associated tap locations, analog multipliers which multiply the tap signals present at the tap locations by tap weight signals to generate product signals and a summer which sums the product signals to generate an equalized output signal. A self-synchronization circuit, responsive to the main tap of the equalizer, synchronizes the data recovery process used by the channel with the rate of the readback signals provided to the channel. The self-synchronization circuit includes peak detection circuitry which uses the main tap signal from the equalizer, as well as the differentiated main tap signal, to detect peaks in the readback signal indicative of magnetic transitions in order to generate timing error signals used to control the generation of a channel clock by a voltage controlled oscillator. A programmable delay allows fine adjustment of the phase of the channel clock to optimize data recovery of the channel, with the programmable delay being calibrated during receipt of sector preamble signals.

Self-synchronization in a magnetic recording channel utilizing

An analog, adaptive generalized transversal equalizer for use in the filtering system of a disc drive PRML read channel, the transversal equalizer employing the use of non-ideal delay elements. The filtering system comprises the equalizer connected in series with an adaptive, analog prefilter. The prefilter is comprised of a plurality of serially connected, adaptive, analog filter stages having variable transfer functions determined by adaptive parameter signals received by the filter stages. The generalized transversal equalizer comprises a plurality of serially connected, adaptive, analog low pass filters, having taps on either side of each low pass filter, a plurality of multipliers that receive signals at the tap locations of the delay circuit, and a summing circuit that receives the outputs of the multipliers. The transfer functions of the delay circuit are continuously variable in relation to adaptive parameter signals received by the delay circuit and the coefficients of multiplication are variable in relation to the adaptation process.

Adaptive analog transversal equalizer

Apparatus for performing time and frequency-domain filtering in a sampled communication channel for the transmission of binary information. A received signal is provided to a double-domain, analog transversal equalizer comprising a plurality of serially connected, active, analog filter sections with associated tap locations, each filter section having a programmable frequency response and adaptively controlled one-bit delay. The filter sections provide sequential, cumulative frequency domain filtering as the received signal propagates through the equalizer. The transfer function of each filter section has a linear phase polynomial denominator and a real (at s=j.omega.) polynomial numerator, facilitating independent control of the delay and frequency response of each filter section. A plurality of analog multipliers multiply signals present at the tap locations by analog tap weight signals to generate a plurality of product signals, and an analog summer adds the product signals to generate an output filtered signal before sampling occurs. An LMS error-based adaptive tap weight control circuit iteratively generates optimal analog tap weight signals, a delay control circuit provides the necessary timing signals at the bit-rate to control the time delay of each analog filter section and a location of zeros circuit controls the location of zeros in the transfer function, and hence the frequency response, of each filter section. The double-domain transversal equalizer provides aperiodic and controlled frequency response at low frequencies and does not require a noise suppressing prefilter.

Frequency and time domain adaptive filtration in a sampled communication

A disc drive system includes a plurality of subsystems. At least one of the subsystems includes a filter which is completely integrated using a synthetic integrated circuit element.

Fully integrated programmable filters for disc drive subsystems

An adaptive, analog filter system of a PRML [PARTIAL RESPONSE MAXIMUM LIKELIHOOD ] read channel of a disc drive comprising an adaptive, analog transversal equator connected in series with an adaptive, analog prefilter. The prefilter is comprised of a plurality of serially connected, adaptive, analog filter stages having variable transfer functions determined by adaptive parameter signals received by the filter stages. The transversal equalizer is comprised of a delay circuit, comprised of a plurality of serially connected, adaptive, analog sixth order low pass filters, that is tapped to either side of each low pass filter, a plurality of analog multipliers that receive signals at the tap locations of the delay circuit, and a summing circuit that receives the outputs of the multipliers. The transfer functions of the sixth order low pass filters are continuously variable in relation to adaptive parameter signals received by the low pass filters and the gains of the multipliers are continuously variable in relation to tap weights received by the multipliers.

Communication channel with adaptive analog transversal equalizer

Method and apparatus for controlling the timing of the sampling of signals and signal amplitude in a PRML read channel. A VCO generates a read clock and a clock generator connected to the VCO generates even and odd clock signals corresponding to even and odd cycles of operation of the VCO. Serially connected even sample and hold circuits respond to clock signals to store samples of the read channel signal taken during successive odd cycles and serially connected odd sample and hold circuits store samples taken during successive even cycles. Comparator circuits compare the samples taken in each cycle to reference signals and the comparisons are clocked through two stage, even and odd shift registers to provide estimates of the presence or absence of nonzero samples for each even and odd cycle. Even and odd time error generators connected to the sample and hold circuits and, via AND gates enabled during even and odd cycles respectively, to the shift registers, generate even and odd time error signals from the samples and estimates during even and odd cycles respectively. An adder transmits the even and odd time error signals to the VCO input. Even and odd gain error generators connected to the sample and hold circuits and the AND gates generate even and odd gain error signals transmitted to a variable gain amplifier in the read channel.

Timing and gain control circuit for a PRML read channel

A maximum likelihood detector for a disc drive in which data files are stored along tracks as a sequence of magnetically written data elements that give rise to a signal in the disc drive read chapel. The detector includes even and odd Viterbi decoders that determine the most likely even and odd subsequences of data elements from even and odd samples of the signal and a postcoder that generates the most likely sequence of bits of encoded user data from the subsequences. Each Viterbi decoder includes an analog adder and an analog subtracter for generating the sums and differences of each sample and a reference signal, a sample and hold circuit codected to the adder and subtracter to receive the sums and differences, a difference circuit that generates the difference between the contents of the sample and hold circuit and each sample, a comparator assembly that generates a two bit merge indicator signal from the output of the difference circuit and the reference signal, AND gates that transmit bits of the indicator signal to switches in the sample and hold circuit for entering the sum or difference of the sample and reference signal into the sample and hold circuit, a shift register having interstate decoders that transmit logical 1's in response to a specific nonzero bit of the merge indicator signal and an indicator bit while otherwise transmitting a logic value determined by the logic value received from a preceding stage of the shift register and a pointer for generating indicator bits for each sample for which the merge indicator signal is logical 00.

Maximum likelihood detector for a disc drive PRML read channel

Methods and apparatus are disclosed which utilize isotropic/perpendicular medium for performing high density digital magnetic recording. According to the preferred embodiment of the invention, the l's of a binary code are deeply imprinted on the medium by switching off the current in the winding of a magnetic ring head. The l's so imprinted on the medium are each represented by a copy of a part of the fringing field of the ring head. Each imprinted field has the appearance of a 'horseshoe' pattern of magnetization. During readback these imprinted patterns correlate extremely well with the sensitivity function (the fringing field) of the ring head/readback transducer. The invention utilizes this inherently present correlation, together with a combination of longitudinal and vertical recording techniques, to provide methods and apparatus well suited to locate signals buried in noise and yield improved overall readback performance in a high density environment. Additionally, following the imprint of each horseshoe, the preferred embodiment of the invention provides for the resumption of current flow, with opposite polarity, as the imprinted pattern(s) moves downstream. This technique continues the perpendicular magnetization at the trailing edge of a previously formed horseshoe pattern and fills voids in magnetization on the medium.

Methods and apparatus for performing high density

A phase lock loop includes a phase shift apparatus to provide a plurality (i.e., four) phase-shifted clock signals from the VCO. A phase selector is responsive to a triggering signal from a one-shot multivibrator to select the one phase-shifted clock signal next following termination of the trigger signal. The one-shot is responsive to a change between the read and write mode to initiate operation of the phase selector. As a result, the initial phase error between the input signal (read pulses or write clock) and the clock signal of the phase lock loop is no more than 1/8 window.

Phase lock loop

A 1,7 decoder is repeatedly initialized during reading of the synchrofield of the record. The decoder includes an oscillator responsive to the record to produce a binary read signal having a frequency f. A first divider produces a source data clock signal having a frequency 2/3 f. A second divider produces a data partition clock signal having a frequency 1/3 f. A phase synchronizer is responsive to the data partition clock signal to synchronize the source data clock signal. An initializer is responsive to the read signal recovered from the preamble of the record to synchronize the data partition clock signal.

Self-initializing 1,7 code decoder with low sensitivity to errors in

A 3/2 frequency divider employs two D-type flip-flops, an OR gate and an AND gate arranged to respond to an input signal at a frequency f to derive an output signal at a frequency 2/3 f. The frequency divider is employed in a code converter to encode or decode 1, 7, 2, 3 codes.

3/2 Frequency divider

An encoding/decoding system for 1,7,2,3 codes employs an oscillator having a frequency f and dividers providing signals at frequencies equal to 1/3 f and 2/3 f. A code converter is responsive to the three signals to encode or decode data. A 3/2 frequency divider employs two D-type flip-flops, an OR gate and an AND gate arranged to respond to an input signal at a frequency f to derive an output signal at a frequency 2/3 f.

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Oklahoma City, OK, United States of America

Vadim B Minuhin