Altera Corporation

Vadali Mahadev

Bruce Euzent

Wen-chou Vincent Wang

Yuan Hang Li

Kaushik Chanda

Mahesh A Iyer

Ravi Prakash Gutala

Archanna Srinivasan

Gurvinder Tiwana

Ronald M Beach

Rajiv Mongia

Srikanth Darbha

Roy Wei-Guang Wu

Jeffrey Barton

Anil Pannikkat

Ganesh Sure

Tomas Jonsson

Systems and methods are provided for generating a circuit design for an integrated circuit using a circuit design tool. The circuit design tool determines maximum junction temperatures for circuit blocks in the circuit design for the integrated circuit. The circuit design tool determines defects values for the circuit blocks using the maximum junction temperatures for the circuit blocks. The circuit design tool determines a defects value for the circuit design based on the defects values for the circuit blocks. The circuit design tool determines a maximum junction temperature for the circuit design based on a comparison between the defects value for the circuit design and a target defects value for the circuit design. The circuit design tool can dynamically reconfigure configurable logic circuit blocks to improve the power, the performance, and the thermal profile to achieve an optimal junction temperature per circuit block.

Systems and methods for circuit design dependent programmable maximum junction temperatures

A test system for testing an integrated circuit package is provided. The test system may include a test board on which a package under test can be mounted, a test box for gathering desired measurements on the package under test, and a test host for automatically controlling the test box during testing. The test box may be coupled to row multiplexing circuitry and column multiplexing circuitry for selectively addressing one or more daisy-chained nets in the package under test. The test box may also be coupled to a source measurement unit (SMU) component that provides current source signals to the package under test and to a digital multimeter (DMM) component that provides voltage sense signals to the package under test. Arranged in this way, the test system can be configured to perform automated I-V curve tracing, resistance measurements, open/short circuit detection, and monitoring of other package-level manufacturing defects.

Methods and apparatus for automated integrated circuit package testing

Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.

Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate

An apparatus performs reliability assessment of electronic hardware. The apparatus includes a test assembly. The test assembly includes at least one programmable logic device (PLD). The PLD is configured to provide a logic function, such as the function of a plurality of inverters coupled in a cascade manner. The apparatus further includes a signal source coupled to the test assembly. The signal source provides a stimulus signal to the test assembly. The apparatus also includes a signal monitor coupled to the test assembly. The signal monitor monitors a response signal generated by the test assembly.

Apparatus and methods for assessing reliability of assemblies using programmable logic devices

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Vadali Mahadev