Chip Express (israel) Ltd.

Quick Technologies Ltd.

Other

Elron Electronic Industries Ltd.

Uzi Yoeli

Zvi Orbach

Meir I Janai

Eran Rotem

Tomer Refael Ben-Chen

Gideon Amir

Lior Amarilio

Yehuda Yizraeli

Lior Amrilio

Richard Stephen Phillips

A customizable integrated circuit including a substrate, a plurality of logic units formed on the substrate and a plurality of metal routing layers formed on the substrate for interconnecting the plurality of logic units. The plurality of metal routing layers includes a first routing layer including a plurality of elongate conductors extending generally in a given direction, a second routing layer including a plurality of transversely extending conductors, each adapted for interconnecting a termination of one of the plurality of elongate conductors to a beginning of another one of the plurality of elongate conductors and at least a third routing layer, including a plurality of local routing conductors, a plurality of customizable connections between pairs of the plurality of elongate conductors via individual ones of the plurality of transversely extending conductors and customizable connections between individual elongate conductors and a plurality of individual local routing conductors.

Single metal programmability in a customizable integrated circuit device

A customizable integrated circuit including a plurality of electrically conducting routing layers formed on a substrate for interconnecting a plurality of logic units formed on the substrate, including a first routing layer including a plurality of elongate conductors extending generally in a given direction, a second routing layer including a plurality of transversely extending conductors, each adapted for interconnecting a termination of one of the plurality of elongate conductors to a beginning of another one of the plurality of elongate conductors; and at least a third routing layer including a plurality of local routing conductors, a plurality of customizable connections, preferably arranged generally in at least one row, between pairs of the plurality of elongate conductors via individual ones of the plurality of transversely extending conductors and, preferably, customizable connections between individual ones of the plurality of elongate conductors and a plurality of individual ones of the local routing conductors.

Configurable cell for customizable logic array device

This invention discloses an integrated circuit device including transistors having predetermined upper voltage limits, a multi-layer metal interconnect structure connecting the transistors to each other and to an external voltage source having a voltage in excess of the predetermined upper voltage limits of a first plurality of the transistors, and a voltage reducer connected along the interconnect structure between the external voltage source and the first plurality of the transistors.

Low voltage device operable with a high voltage supply

A customizable gate array device including a customizable gate array portion and a customizable memory portion.

Customizable integrated circuit device

A customizable logic array device including an array of identical multiple input, function selectable logic cells comprising a first conductive layer, application configurable interconnection apparatus selectably interconnecting the multiple input, function selectable logic cells, the application configurable interconnection apparatus comprising at least two conductive layers.

Customizable logic array device

This invention discloses a gate array device, useful either as a configurable gate array device or a compact gate array device, comprising an array of two-gate logic cells arranged in columns, a metal grid interconnecting said logic cells into clusters of macrocells, said grid comprising a bottom metal layer and at least one metal layer disposed over the bottom metal layer, power and ground lines formed of said bottom metal layer, extending generally parallel to said columns and a routing grid interconnecting said clusters of macrocells, said routing grid comprising parallel metal tracks crossing said columns of logic cells, and wherein no more than two of said parallel metal tracks are employed to connect to each logic cell.

Mapping of gate arrays

A very high speed customizable logic array device comprising:

High speed customizable logic array device

A cell forming part of a customizable logic array and including at least first and second different multiplexers, an output of the first multiplexer being connected to an input of the second multiplexer.

Cell forming part of a customizable logic array

A selectably customizable semiconductor device including a first metal layer disposed in a first plane and including first elongate strips extending parallel to a first axis, a second metal layer disposed in a second plane generally parallel to and electrically insulated from said first plane and including second elongate strips extending parallel to a second axis, the second axis being generally perpendicular to the first axis, whereby a multiplicity of elongate strip overlap locations are defined at which the elongate strips of the first and second metal layers overlap in electrical insulating relationship;

Routing structure for a customizable integrated circuit

A controlled slew rate buffer is disclosed which comprises a driver receiving voltage along a voltage supply line and includes feedback apparatus which senses the noise level along the voltage supply line and slows the speed of the buffer when the noise level passes a given threshold. The driver comprises at least one of (1) first and second VSS voltage sources and (2) first and second VDD voltage sources.

Controlled slew rate buffer

A selectably customizable semconductor device including a first metal layer disposed in a first plane and including first elongate strips extending parallel to a first axis, a second metal layer disposed in a second plane generally parallel to and electrically insulated from the first plane and including second elongate strips extending parallel to a second axis, the second axis being generally perpendicular to the first axis, whereby a multiplicity of elongate strip overlap locations are defined at which the elongate strips of the first and second metal layers overlap in electrical insulating relationship, the first metal layer including a plurality of fusible conductive bridges joining adjacent pairs of the first elongate strips, the fusible conductive bridges including first and second fusible links, the first metal layer also including a plurality of branch strips, each branch strip connecting one of the fusible conductive bridges at a location intermediate the first and second fusible links to a branch overlap location spaced from the multiplicity of elongate strip overlap locations, an electrical connection being formed between the first metal layer and the second metal layer at each of the branch overlap locations.

Customizable semiconductor devices

A selectably customizable semiconductor device first and second metal layers disposed in respective first and second planes and including respective first and second elongate strips, conductive branches being provided in association with the elongate strips.

Growing community of inventors

Haifa, Israel

Uzi Yoeli