Infineon Technologies Austria Ag

Infineon Technologies Ag

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Infineon Technologies Dresden Gmbh

Infineon Technologies Dresden Gmbh & Co . Kg

Uwe Wahl

Armin Willmeroth

Franz Hirler

Hans-Joachim Schulze

Markus Schmitt

Jens-Peer Stengl

Anton Mauder

Carolin Tolksdorf

Markus Hammer

Winfried Kaindl

Thorsten Meyer

Hans Weber

Joachim Weyers

Martin Kerber

Bernhard Knott

Andreas Strasser

Stefan Willkofer

Michael Rüb

Ralf Otremba

Gerald Deboy

Dirk Ahlers

Carsten Schaeffer

Frank Dieter Pfirsch

Martin Feldtkeller

Rolf Weis

Klaus Schiess

Stefan Tegen

Armin Tilke

Marcus Nuebling

Dominic Maier

Thomas Kilger

Peter Kanschat

Michael Rueb

Uwe Kirchner

Bernd Stadler

Ulrich Wachter

Ralf Henninger

Ralf Rudolf

Andreas Schloegl

Katarzyna Kowalik-Seidl

Dirk Priefert

Jenö Tihanyi

Carsten Schäffer

Ernst Katzmaier

Patrick Schindler

Ulrich Froehler

Felix Grawert

Andreas Schlögl

Rene Mente

Veronika Huber

Andreas Boehm

Miguel Cuadron Marion

A method includes partly removing a supporting layer arranged between a first semiconductor layer and a second semiconductor layer using an etching process to form at least one undercut between the first semiconductor layer and the second semiconductor layer, at least partly filling the at least one undercut with a first material having a higher thermal conductivity than the supporting layer, and forming a sensor device in or on the second semiconductor layer. Semiconductor arrangements and devices produced by the method are also described.

Method for producing a semiconductor arrangement

A charge-compensation semiconductor device includes a source metallization spaced apart from a gate metallization, and a semiconductor body including opposing first and second sides, a drift region, a plurality of body regions adjacent the first side and each forming a respective first pn-junction with the drift region, and a plurality of compensation regions arranged between the second side and the body regions. Each compensation region forms a respective further pn-junction with the drift region. A plurality of gate electrodes in Ohmic connection with the gate metallization is arranged adjacent the first side and separated from the body regions and the drift region by a dielectric region. A resistive current path is formed between one of the gate electrodes and a first one of the compensation regions, or between the first one of the compensation regions and a further metallization spaced apart from the source metallization and the gate metallization.

Charge-compensation semiconductor device and a manufacturing method therefor

A super junction semiconductor device includes an impurity layer of a first (conductivity) type formed in a semiconductor portion having first and second parallel surfaces, a super junction structure between the first surface and impurity layer and including first columns of the first type and second columns of a second (conductivity) type, a body zone of the second type formed between the first surface and one of the second columns at least partially in the vertical projection of the second columns, and a field extension zone of the second type electrically connected to the body zone and arranged in the vertical projection of one of the columns. An area impurity density in the field extension zone is between 1&#xd7;10and 5&#xd7;10cm. A mean net impurity concentration in the field extension zone is higher than in the second columns and lower than in the body zone.

Super junction semiconductor device with field extension zones

Various embodiments provide an electronic device, wherein the electronic device comprises a mounting surface configured to mount the electronic device to an external structure and having a first size; a backside electrode having a second size and having arranged thereon a die electrically connected to the backside electrode; wherein the first size is at least three times the second size.

Electronic device and method of manufacturing the same

Semiconductor component comprising at least two semiconductor regions are disclosed. In one embodiment the semiconductor regions of the semiconductor component are electrically isolated from one another by an insulator, and a deposited, patterned, metallic layer extends over the semiconductor regions and over the insulator.

Semiconductor component with regions electrically insulated from one another and method for making a semiconductor component

A super junction semiconductor device includes a semiconductor portion with first and second surfaces parallel to one another and including a doped layer of a first conductivity type formed at least in a cell area. Columnar first super junction regions of a second conductivity type extend in a direction perpendicular to the first surface and are separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A first electrode structure directly adjoins the first surface and a second electrode structure directly adjoins the second surface. The first electrode structure has a first thickness and the second electrode structure has a second thickness. A sum of the first and second thicknesses is at least 20% of the thickness of the semiconductor portion between the first and second surfaces.

Super junction semiconductor device having columnar super junction regions extending into a drift layer

A trench transistor having a semiconductor body includes a source region, a body region, a drain region electrically connected to a drain contact, and a gate trench including a gate electrode which is isolated from the semiconductor body. The gate electrode is configured to control current flow between the source region and the drain region along at least a first side wall of the gate trench. The trench transistor further includes a doped semiconductor region having dopants introduced into the semiconductor body through an unmasked part of the walls of a trench.

Trench transistor having a doped semiconductor region

A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal. The half-bridge circuit further includes a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.

Half-bridge circuit with a low-side transistor and a level shifter transistor integrated in a common semiconductor body

A signal transmission arrangement is disclosed. A voltage converter includes a signal transmission arrangement.

Signal transmission arrangement

A super junction semiconductor device includes a semiconductor portion with a first surface and a second surface parallel to the first surface. The semiconductor portion includes a doped layer of a first conductivity type formed at least in a cell area. The super junction semiconductor device further includes columnar first super junction regions of a second, opposite conductivity type extending in a direction perpendicular to the first surface and separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A distance between the first super junction regions and the second surface does not exceed 30 &#x3bc;m.

Super junction semiconductor device having columnar super junction regions

A super junction semiconductor device includes a semiconductor portion with parallel first and second surfaces. An impurity layer of a first conductivity type is formed in the semiconductor portion. Between the first surface and the impurity layer a super junction structure includes first columns of the first conductivity type and second columns of a second conductivity type. A sign of a compensation rate between the first and second columns may change along a vertical extension of the columns perpendicular to the first surface. A body zone of the second conductivity type is formed between the first surface and one of the second columns. A field extension zone of the second conductivity type may be electrically connected to the body zone or a field extension zone of the first conductivity type may be connected to the impurity layer. The field extension zone improves the avalanche characteristics of the semiconductor device.

Semiconductor device with a super junction structure having a vertical impurity distribution

The present disclosure provides a semiconductor device and an integrated apparatus having the same. The semiconductor device includes a substrate, a buffer layer on the substrate, a compensation area which includes a p-region and a n-region on the buffer layer, and a transistor cell on the compensation area. The transistor cell includes a source region, a body region, a gate electrode and a gate dielectric formed at least between the gate electrode and the body region. The gate dielectric has a thickness in a range of 12 nm to 50 nm.

Semiconductor device and integrated apparatus comprising the same

A semiconductor device, a method of manufacturing a semiconductor device and a method for transmitting a signal are disclosed. In accordance with an embodiment of the present invention, the semiconductor device comprises a first semiconductor chip comprising a first coil, a second semiconductor chip comprising a second coil inductively coupled to the first coil, and an isolating intermediate layer between the first semiconductor chip and the second semiconductor chip.

Semiconductor device and method of manufacture thereof

A semiconductor device includes transistor cells with vertical channels perpendicular to a first surface of a semiconductor portion. A buried compensation structure in the semiconductor portion between the transistor cells and a second surface of the semiconductor portion parallel to the first surface includes first areas and second areas. The first and second areas are alternatingly arranged along a lateral direction parallel to the first surface. A contiguous impurity layer of a first conductivity type separates the transistor cells from the buried compensation structure.

Semiconductor device with vertical transistor channels and a compensation structure

A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

Molded semiconductor package with backside die metallization

Growing community of inventors

Munich, Germany

Uwe Wahl