International Business Machines Corporation

Uwe Schwiegelshohn

Martin Aureliano Hassner

Shmuel Winograd

Norman Ken Ouchi

Charles Edwin Cox

Ehud Dov Karnin

Tetsuya Tamura

Gerhard P Fettweis

Luke C Lang

An apparatus and method for detecting analog signals representing patterns of n-bit RLL-encoded data read from a data storage device. R integrators each integrate the analog signal over successive time periods consisting of a preselected number n of bit cycles, where n&gt;1, weighted by a preselected set of n orthogonal signals that are staircase functions which vary each bit cycle to provide R integrated weighted outputs. The R integrated weighted outputs are converted by a lookup table or read-only memory into an n-bit digital representation corresponding to a unique one of the n-bit analog data patterns.

Signal processing channel with high data rate and low power consumption

The error correction code capability of the linear recording density of a zone of contiguous recording tracks on a surface or volume having at lest two zones of different average linear recording density is adjusted. Each zone has associated therewith a parameter pair (r,R) defining the number of error correction bytes r to be appended to data blocks to form a codeword written to tracks within the zone and the number R.ltoreq.(r/2-1) of correctable errors in the event of a non-zero remainder detected upon readback of a codeword from a track within the zone. The r parameter controls the length of a shift register type encoder syndrome generator.

Location dependent variable error correction processing for multi-track

A composite encoder/syndrome generating circuit computes both check symbols and error syndromes using a single set of multiplier devices with varying tap weights having values that provide a maximum preselected error correction capability but is readily adjustable, such as by programmable latches, to eliminate from the circuit selectable multiplier devices to reduce the error correction capability without requiring a change in the tap weight values. The circuit may be used to increase or decrease error correction capability (a) according to which of a plurality of concentric bands of recording tracks is being accessed in a banded direct access data storage device, (b) according to noise level as sensed in a data communications channel having an output subject to noise, or (c) according to changes in sending rates in a sending device that sends data at variable rates.

Adjustable error-correction composite Reed-Solomon encoder/syndrome

Apparatus and method for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code. Circuitry implements two computation sequences. One of these executes three multiplication operations and the other executes five multiplication operations, 2t iterations of these two sequences being required to decode t symbols in error. These sequences are coupled such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in the other sequence being paired with a multiplication operation in the next iteration of the one sequence. During one of the paired multiplication operations an inverse table look up operation is executed, and during another of the multiplication operations an addition operation is executed. Two consecutive executions of the other sequence are prevented.

Modular implementation for a parallelized key equation solver for linear

An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer compresses an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.

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Uwe Schwiegelshohn