Infineon Technologies Ag

Other

Qimonda Ag

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Infineon Technologies North America Corp.

Namlab Ggmbh

Infineon Ag

Uwe Schroeder

Helmut Horst Tews

Stephan Kudelka

Stefan Jakschik

Irene Lennox McStay

Tim Boescke

Jeffrey P Gambino

Ramachandra Divakaruni

Gary Bela Bronner

Richard Anthony Conti

Rama Divakaruni

Harald Seidl

Thomas Hecht

Mary Elizabeth Weybright

Peter D Hoh

Annette Saenger

Johannes Heitmann

Jack Allan Mandelman

Oleg Gluschenkov

Michael Patrick Chudzik

Rolf Weis

Bernhard Sell

Rajarao Jammy

Albert Birner

Matthias Goldbach

Benjamin Szu-Min Lin

Joseph Francis Shepard, Jr

Martin Gutsche

Han-jin Lim

Youn-soo Kim

Martin Popp

Alexander Michaelis

Kyu-Ho Cho

Dirk Schumann

Kristin Schupke

Elke Erben

Jochen Schacht

Karen Lynne Holloway

Jean-Marc Rousseau

Kil-Ho Lee

Raj Jammy

Stephen Rahn

Joerg Schumann

Daniel Koehler

Manfred Hauf

Gerd Fehlauer

Gabriela Brase

Steve Knebel

Lars Oberbeck

Alejandro Avellan

A capacitor can include a crystallized metal oxide dielectric layer having a first dielectric constant and an amorphous metal oxide dielectric layer, on the crystallized metal oxide dielectric layer, where the amorphous metal oxide dielectric layer has a second dielectric constant that is less than the first dielectric constant and is greater than a dielectric constant of aluminum oxide.

Capacitors including amorphous dielectric layers and methods of forming the same

The present invention refers to an electrode comprising a first metallic layer and a compound comprising at least one of a nitride, oxide, and oxynitride of a second metallic material.

Electrode of an integrated circuit

A capacitor structure comprises a first and a second electrode of conducting material. Between the first and second electrodes, an atomic layer deposited dielectric film is disposed, which comprises zirconium oxide and a dopant oxide. Herein, the dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, while the dielectric film comprises a dopant content of 10 atomic percent or less of the dielectric film material excluding oxygen. A process for fabricating a capacitor comprises a step of forming a bottom electrode of the capacitor. On the bottom electrode, a dielectric film comprising zirconium oxide is deposited, and a step for introducing a dopant oxide into the dielectric film performed. On the dielectric structure, a top electrode is formed. The dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, whereas the dielectric structure deposited comprises a dopant content of 10 atomic percent or less of the deposited material excluding oxygen.

Zirconium oxide based capacitor and process to manufacture the same

The present invention relates to a method for depositing a dielectric material comprising a transition metal compound. After providing a substrate, a first pre-cursor comprising a transition metal compound and a second pre-cursor predominantly comprising at least one of water vapour, ammonia and hydrazine are successively applied on the substrate for forming a first layer of transition metal containing material. In a next step the first pre-cursor and a third pre-cursor comprising at least one of ozone and oxygen are successively applied on the first layer for forming a second layer of the transition metal containing material.

Deposition method for a transition-metal-containing dielectric

An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric () and at least one connection electrode () are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric () or the connection electrode () are formed in such a manner that transient polarization effects are prevented or at least reduced.

Method for fabricating an electrical component

A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.

Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices

A photomask with desired illumination conditions can be constructed by combining a base pattern of openings with an assist pattern which includes openings that are offset from respectively corresponding openings of the base pattern by a preset angular distance.

Effective assist pattern for nested and isolated contacts

A method for eching a recess in a polysilicon region of a semiconductor device by applying a solution of NH OH in water to the polysilicon.

Etch process for recessing polysilicon in trench structures

Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

Low resistivity deep trench fill for DRAM and EDRAM applications

A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

Process flow for thick isolation collar with reduced length

The vertical DRAM capacitor with a buried LOCOS collar characterized by: a self-aligned bottle and gas phase doping; no consumption of silicon at the depth of the buried strap; no reduction of trench diameter; and a nitride layer to protect trench sidewalls during gas phase doping.

Method of preparing buried LOCOS collar in trench DRAMS

An interconnection pattern is formed over the surface of a silicon wafer in which both the vias and the trenches of the pattern are filled with copper. The process of filling the vias and trenches involves use of a silicon nitride film as an etch stop and the filling of the vias with an anti-reflection coating.

'Via first' dual damascene process for copper metallization

Rough oxide hard mask for DT surface area enhancement for DT DRAM

Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

Modified gate processing for optimized definition of array and logic devices on same chip

A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.

Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation

Growing community of inventors

Dresden, Germany

Uwe Schroeder