Infineon Technologies Ag

Infineon Technologies Dresden Gmbh

Infineon Dresdon Gmbh & Co. Kg

Uwe Rudolph

Thoralf Kautzsch

Boris Binder

Mirko Vogt

Maik Stegemann

Alessia Scire

Marc Probst

Torsten Helm

Stefan Tegen

Heiko Froehlich

Marko Lemke

Sebastian Pregl

Stefan Kolb

Armin Tilke

Steffen Bieselt

Martin Seck

Andre Roeth

Marco Mueller

Lothar Brencher

Frank Hoffmann

Frank Hoffman

Maik Stegememann

A light emitter device contains a heater structure configured to emit light if a predefined current flows through the heater structure. The heater structure is arranged at a heater carrier structure. The light emitter device contains an upper portion of a cavity located vertically between the heater carrier structure and a cover structure. The light emitter device contains a lower portion of the cavity located vertically between the heater carrier structure and at least a portion of a carrier substrate. The heater carrier structure contains a plurality of holes connecting the upper portion of the cavity and the lower portion of the cavity. A pressure within the cavity is less than 100 mbar.

Light emitter devices, optical filter structures and methods for forming light emitter devices and optical filter structures

In a method for producing a buried cavity in a semiconductor substrate, trenches are produced in a surface of a semiconductor substrate down to a depth that is greater than cross-sectional dimensions of the respective trench in a cross section perpendicular to the depth, wherein a protective layer is formed on sidewalls of the trenches. Isotropic etching through bottom regions of the trenches is carried out. After carrying out the isotropic etching, the enlarged trenches are closed by applying a semiconductor epitaxial layer to the surface of the semiconductor substrate.

Producing a buried cavity in a semiconductor substrate

A method for forming a MEMS device may include performing a silicon-on-nothing process to form a cavity in a monocrystalline silicon substrate at a first depth relative to a top surface of the monocrystalline silicon substrate; forming, in an electrically conductive electrode region of the monocrystalline silicon substrate, an electrically insulated region extending to a second depth that is less than the first depth relative to the top surface of the monocrystalline silicon substrate; and etching the monocrystalline silicon substrate to expose a gap between a first electrode and a second electrode, wherein the second electrode is separated from the first electrode, within a first depth region, by a first distance defined by the electrically insulated region and the gap, and wherein the second electrode is separated from the first electrode, within a second depth region, by a second distance defined by the gap.

Forming an offset in an interdigitated capacitor of a microelectromechanical systems (MEMS) device

A semiconductor device includes a semiconductor body having a main surface and a rear surface opposite the main surface, and a trench that extends from the main surface of the semiconductor body towards the rear surface, the trench having an upper trench portion and a lower trench portion, the trench having a width measured along a plane parallel to the main surface. The upper trench portion includes curved sidewalls that that bow outward from a bottom of the upper trench portion. The lower trench portion includes generally planar sidewalls that extend from bottom of the upper trench portion at a first depth into the semiconductor body along the first direction to a contact region. An electrically conductive contact electrode is within the trench, is electrically insulated from the semiconductor body along sidewalls of the trench, and electrically connects to the semiconductor body at a bottom of the trench.

Integrated circuit and method of forming an integrated circuit

A method for manufacturing a plurality of nanowires, the method including: providing a carrier comprising an exposed surface of a material to be processed and applying a plasma treatment on the exposed surface of the material to be processed to thereby form a plurality of nanowires from the material to be processed during the plasma treatment.

Apparatus comprising a plurality of nanowires

An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.

Method for manufacturing a plurality of nanowires

According to various embodiments, a method for processing a wafer may include: forming at least one hollow chamber and a support structure within the wafer, the at least one hollow chamber defining a cap region of the carrier located above the at least one hollow chamber and a bottom region of the carrier located below the at least one hollow chamber and an edge region surrounding the cap region of the carrier, wherein a surface area of the cap region is greater than a surface area of the edge region, and wherein the cap region is connected to the bottom region by the support structure; removing the cap region in one piece from the bottom region and the edge region.

Wafer, a method for processing a wafer, and a method for processing a carrier

Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.

Method of fabricating isolating semiconductor structures using a layout of trenches and openings

Semiconductor manufacturing and semiconductor device with semiconductor structure

In the inventive method of producing a base terminal structure for a bipolar transistor, an etch stop layer is applied on a single-crystal semiconductor substrate, a poly-crystal base terminal layer is produced on the etch stop layer and an emitter window is etched in the base terminal layer using the etch stop layer as an etch stop.

Polysilicon bipolar transistor and method of manufacturing it

The invention relates to a method for producing trenches for manufacturing storage capacitors in DRAM cell configurations. In the method, a two-stage hard mask having a first mask layer ( ) and an underlying second mask layer ( ) is used. A resist mask is applied to the mask layers ( ). The trenches are structured by etching processes, in which, in a first etching process, the first mask layer ( ) is etched selectively with respect to the resist mask, and in a second etching process, the second mask layer ( ) is etched selectively with respect to the first mask layer ( ).

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Dresden, Germany

Uwe Rudolph