Advanced Micro Devices Corporation

Globalfoundries Inc.

Advance Micro Devices, Inc.

Advanced Micro Systems, Inc.

Uwe Kranich

David S Christie

A processor comprises a first mode of operation and a second mode of operation. A state of the processor in the first mode of operation comprises a first plurality of variables. The first plurality of variables comprises a return address. A state of the processor in the second mode of operation comprises a second plurality of variables in addition to the first plurality of variables. The processor is configured to perform, in case of an interrupt or exception occurring during the second mode of operation, the steps of saving the second plurality of variables and the return address to a buffer memory, replacing the return address with an address of a trampoline instruction, and switching into the first mode of operation. These steps are performed independently of an operating system. The trampoline instruction is adapted to switch the processor from the first mode of operation to the second mode of operation, to read the second plurality of variables and the return address from the buffer memory and to jump to the return address.

Processor comprising a first and a second mode of operation and method of operating the same

A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables. A system includes a master processor having a first state, a slave processor having a second state, and a buffer memory. The system is operable to switch from a parallel mode to a serial mode responsive to an interrupt or exception and save the states to the buffer memory. Responsive to the interrupt or exception occurring in the slave processor, the system sets at least one variable in the first state to that of a variable in the second state. Responsive to the interrupt or exception occurring in the master processor, the system saves a first return address from the first state and the second state to the buffer memory and replaces the first return address with an address of a trampoline instruction. The trampoline instruction switches the system to the parallel mode of operation and reads the second state and the first return address from the buffer memory.

Transparent return to parallel mode by rampoline instruction subsequent to interrupt processing to accommodate slave processor not supported by operating system

A system and method for generating images of three-dimensional objects. The system includes one or more tracing processors, and one or more shading processors. Each of the tracing processors may be configured to (a) perform a first set of computations on a corresponding group of primary rays emanating from a viewpoint resulting in a ray tree and a set of one or more light trees for each primary ray of the corresponding group, (b) transfer the ray trees and associated light trees to one of the shading processors, and (c) repeat (a) and (b). Each of the shading processors may be configured to (d) receive ray trees and associated light trees from one of the tracing processors, (e) perform a second set of computations on the received ray trees and associated light trees to determine pixel color values, and (f) repeat (d) and (e) a plurality of times.

System architecture for high speed ray tracing

A mechanism for exception and interrupt handling in multithreaded multiprocessors is provided. The mechanism allows the handling of exceptions and interruptions in a multithreaded multiprocessor computer, while hiding the multiprocessor nature of the computer from the operating system. Generally, when an operating system is cognizant of the multiprocessor nature of a computer, additional overhead may be required when handling exceptions and interruptions. Due to the overhead involved in saving and restoring processing states, the performance of a processor may be significantly impacted. Additional circuitry is provided which allows the multiprocessor nature of the computer to be hidden from the operating system, while minimizing the overhead necessary for proper handling.

Exception handling with reduced overhead in a multithreaded multiprocessing system

A processor architecture containing multiple closely coupled processors in a form of symmetric multiprocessing system is provided. The special coupling mechanism allows it to speculatively execute multiple threads in parallel very efficiently. Generally, the operating system is responsible for scheduling various threads of execution among the available processors in a multiprocessor system. One problem with parallel multithreading is that the overhead involved in scheduling the threads for execution by the operating system is such that shorter segments of code cannot efficiently take advantage of parallel multithreading. Consequently, potential performance gains from parallel multithreading are not attainable. Additional circuitry is included in a form of symmetrical multiprocessing system which enables the scheduling and speculative execution of multiple threads on multiple processors without the involvement and inherent overhead of the operating system. Advantageously, parallel multithreaded execution is more efficient and performance may be improved.

Method and mechanism for speculatively executing threads of instructions

A system and method for transparent handling of extended register states. A set of additional registers, or an extended register file, is added to the base architecture of a microprocessor. The extended register file includes two dedicated registers and a plurality of general-use registers. The extended register file is mapped to a region in main memory. One dedicated register of the extended register file stores the physical base address of the memory region. Another dedicated register of the extended register file is used to store bits to indicate the status of the extended register file. A set of extended instructions is implemented for transferring data to and from the extended register file.

System and method for transparent handling of extended register states

A microprocessor having a standard register set and an extended register set, which is configured to save its state upon suspension of either an extended register process or a standard register processor. The microprocessor is configured to execute both standard register instruction sequences and extended register instruction sequences. A first memory is provided for storing a state of the microprocessor when a standard register instruction set sequence is suspended. The microprocessor further comprises a second memory for storing a microprocessor state upon suspension of the microprocessor executing an extended register instruction set sequence. An extended state save circuit coupled between a microprocessor core and the second memory allows the extended state of the microprocessor to be stored without modification of the operating system. As a result, the extended state of the microprocessor can be saved transparently to the operating system.

Transparent extended state save

A cache memory configured to access stored instructions according to basic blocks is disclosed. Basic blocks are natural divisions in instruction streams resulting from branch instructions. The start of a basic block is a target of a branch, and the end is another branch instruction. A microprocessor configured to use a basic block oriented cache may comprise a basic block cache and a basic block sequence buffer. The basic block cache may have a plurality of storage locations configured to store basic blocks. The basic block sequence buffer also has a plurality of storage locations, each configured to store a block sequence entry. The block sequence entry may comprise an address tag and one or more basic block pointers. The address tag corresponds to the fetch address of a particular basic block, and the pointers point to basic blocks that follow the particular basic block in a predicted order. A system using the microprocessor and a method for caching instructions in a block oriented manner rather than conventional power-of-two memory blocks are also disclosed.

Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks

A processor for executing computer instructions including, in one embodiment, a machine specific register (MSR) which includes a predicated execution field and an instruction decoder. The decoder is coupled to the MSR and configured to detect predicated execution information contained in the computer instruction and to include conditional execution information in the decoded instruction upon detecting an appropriate setting in the predicated execution field of the MSR. The processor further includes a first execution unit. The first execution unit is configured to detect and evaluate the conditional execution information in the decoded instruction and, if present, to execute the decoded instruction only if a condition represented by the conditional execution information is true. In another embodiment, the processor includes a standard register set and an extended register set, which includes the standard register set. The decoder is configured to search the computer instruction for an extended register indicator upon detecting an appropriate setting in the extended register field of the MSR. The decoder is further configured to fetch, upon detecting the extended register indicator, a value from a selected register within the extended register set. If the decoder detects the absence of extended register indicator, a value is fetched from a selected register where the selected register is within the standard register set. In another embodiment, the MSR includes a three register field and the decoder is configured to interpret the computer instruction as containing first and second source register operands and a destination operand if the instruction contains a three register indicator and the three register field is set appropriately.

Processor programably configurable to execute enhanced variable byte

An apparatus and method for reducing the cache miss penalty in a virtual memory system is provided. The virtual memory system includes a processor core which generates virtual addresses and a cache configured to supply information in response to receipt of physical addresses. The apparatus includes a logical-to-physical translation unit which converts the virtual addresses generated by the processor core to physical addresses. The logical-to-physical translation unit includes an accurate translation unit, a speculative translation unit, and a comparing unit. The accurate translation unit accurately converts logical addresses to physical addresses. The speculative translation unit generates and transmits a speculative physical address to the cache before the accurate translation unit completes generation of the accurate physical address. When the accurate translation unit completes generation of the accurate physical address, the comparing unit compares the accurate physical address with the speculative physical address. If the accurate physical address does not match the speculative physical address, the transmission of the speculative physical address to the cache is aborted, and the accurate physical address is transmitted to the cache.

Apparatus and method for reducing the cache miss penalty in a virtual

A memory system for reducing cache snooping overhead for a multilevel cache system has a highest cache level connected to a main memory and a lowest cache level connected to a processor or other memory accessing device. Each intermediate level cache is connected to a cache level one level above and below that cache. The highest cache level detects a memory access on a shared memory bus, and determines if that memory access resides in that cache. If there is a hit in that cache, the highest cache level checks a hit flag for every storage location within that highest level cache to determine if the memory access also hits a storage location within the next lower cache level. If there is a hit in the next lower cache level, that cache also checks a hit flag for every storage location within that cache to determine if the memory access also hits a storage location within the next lower cache level. This process continues until the memory access does not hit a particular cache level or until the lowest cache level is reached.

Method and apparatus for reducing cache snooping overhead in a

A multiple-transaction peripheral bus is provided with multiplexed address and data lines which is particularly adapted for portable applications. The multiple-transaction peripheral bus accommodates compatibility with existing hardware designs for a higher performance bus system with minimal conversion logic. A bus conversion bridge provides an interface between a 32-bit Peripheral Component Interconnect (PCI) bus and a 16-bit transaction Address/Data (A/D) which is associated with half the number of multiplexed address/data lines in comparison with the 32-bit PCI bus. The PCI bus accommodates data transfers between master and slave devices associated therewith, as does the narrower multiple-transaction A/D bus. The bus conversion bridge accommodates data transfers between the two buses, allowing a master device on one bus to communicate with a slave device on the other bus. The bus conversion bridge accomplishes this by 1) splitting both the 32-bit address/4-bit bus command and 32-bit data/4-bit byte enables received from the PCI bus during respective address and data phases into separate 16-bit/2-bit packets, and transmitting these packets over the multiple-transaction A/D bus during separate bus cycles, and 2) assembling multiple 16-bit address/2-bit bus command and multiple 16-bit data/2-bit byte enables received from the multiple-transaction A/D bus during separate bus cycles into single 32-bit/4-bit packets, and transmitting these packets over the PCI bus during respective address and data phases. Thus the bus conversion bridge allows a portable computer system with a narrower, 16-bit multiple-transaction A/D bus to communicate with peripherals on a wider, 32-bit PCI bus.

Computer system employing a bus conversion bridge for interfacing a

A memory system has a level 1 cache and a write cache connected to a processor, wherein the write cache has a memory address range and wherein the processor initiates a write to the write cache which is detected by the write cache. The write cache responds to the write request by storing information into the write cache if the write cache is not already full. If there is no storage location available in the write cache, a message is sent to the level 1 cache notifying that cache of this condition. The write cache responds to requests from the processor to write information stored in particular areas of the write cache into a main memory by placing that information on a external bus to be read by the main memory. The write cache then frees up those storage locations within the write cache to be used for storing subsequent writes requested by the processor.

Write cache for servicing write requests within a predetermined address

An apparatus and method for reducing the time required to supply a processor core with instructions uses a cache memory, a cache controller, and an instruction predecoding unit. When a line of instructions is retrieved into the cache memory, the instruction predecoding unit inspects the instructions in the line to determine if the line contains any nonsequential instructions. The cache controller stores an indication of whether the line contains nonsequential instructions with the line of instructions in the cache memory. If a given line of instructions does not contain any nonsequential instructions, the line of instructions following the given line is retrieved into the cache memory when one of the instructions in the given line is requested by the processor core.

Apparatus and method for reducing read miss latency by predicting

A method and device for avoiding unnecessary data broadcasts by detecting the presence of additional cache-equipped bus-masters is provided. The device includes a master bus-master equipped with a local cache arrangement for caching data originating in a system memory. The master bus-master communicates with the system memory over a bus, and is coupled to a control line at an input. Any cache-equipped slave bus masters that are caching data with the system memory are coupled to the control line by an output and are configured to generate a signal at the output to drive the control line to a predetermined state to indicate that they are caching data. The master bus-master detects the state of the control line and determines whether the data being buffered in its local cache arrangement is shared based upon the state of the control line. If the state of the control line indicates the presence of other cache-equipped bus-masters, the master bus-master automatically broadcasts data that it modifies; otherwise it writes the modified data back to the system memory when the cache space occupied by the modified data is required for new data.

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Kirchheim, Germany

Uwe Kranich