Globalfoundries Inc.

Advanced Micro Devices Corporation

Uwe Griebenow

Jan Hoentschel

Sven Beyer

Thilo Scheiper

Kai Frohberg

Andy C Wei

Katrin Reiche

Heike Berthold

Frank Feustel

Thomas Werner

Martin Gerhardt

Ralf Richter

Maciej Wiatr

Thomas Feudel

Vassilios Papageorgiou

Andreas Kurz

Kerstin Ruttloff

Roman Boschke

Klaus Hempel

Christoph Schwan

Martin Mazur

Wolfram Grundke

Andre Poock

Roland Stejskal

Thilo Sheiper

A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.

Semiconductor device comprising a stacked die configuration including an integrated peltier element

In sophisticated semiconductor devices, the contact structure may be formed on the basis of contact bars formed in a lower portion of an interlayer dielectric material, which may then be contacted by contact elements having reduced lateral dimensions so as to preserve a desired low overall fringing capacitance. The concept of contact bars of reduced height level may be efficiently combined with sophisticated replacement gate approaches.

Contact bars with reduced fringing capacitance in a semiconductor device

Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

Field effect transistors for a flash memory comprising a self-aligned charge storage region

During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability.

High-K gate electrode structure formed after transistor fabrication by using a spacer

In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage

In a stacked semiconductor device, a Peltier element may be incorporated as a distributed element so as to provide active heat transfer from a high power device into a low power device, thereby achieving superior temperature control in stacked device configurations. For example, a CPU and a dynamic RAM device may be provided as a stacked configuration, wherein waste heat of the CPU may be efficiently distributed into the low power memory device.

Semiconductor device comprising a stacked die configuration including an integrated Peltier element

When forming sophisticated high-k metal gate electrode structures, the removal of a dielectric cap material may be accomplished with superior process uniformity by using a silicon dioxide material. In other illustrative embodiments, an enhanced spacer regime may be applied, thereby also providing superior implantation conditions for forming drain and source extension regions and drain and source regions.

Enhanced confinement of sensitive materials of a high-K metal gate electrode structure

The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.

Method for increasing penetration depth of drain and source implantation species for a given gate height

A non-conformal metal silicide in a transistor of recessed drain and source configuration may provide enhanced efficiency with respect to strain-inducing mechanisms, drain/source resistance and the like. For this purpose, in some cases, an amorphizing implantation process may be performed prior to the silicidation process, while in other cases an anisotropic deposition of the refractory metal may be used.

Method for forming a transistor with recessed drain and source areas and non-conformal metal silicide regions

Sophisticated high-k metal gate electrode structures are provided on the basis of a hybrid process strategy in which the work function of certain gate electrode structures is adjusted in an early manufacturing stage, while, in other gate electrode structures, the initial gate stack is used as a dummy material and is replaced in a very advanced manufacturing stage. In this manner, superior overall process robustness in combination with enhanced device performance may be achieved.

High-K metal gate electrode structures formed at different process stages of a semiconductor device

In an integrated circuit device, such as a microprocessor, a device internal optical communication system is provided in order to enhance signal transfer capabilities while relaxing overall thermal conditions. Furthermore, the device internal optical data or signal transfer capabilities may result in superior operating speed and a high degree of design flexibility. The optical communication system may be applied as a chip internal system in single chip systems or as an inter-chip optical system in three-dimensional chip configurations provided in a single package.

Semiconductor device comprising a buried waveguide for device internal optical communication

An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.

Asymmetric transistor devices formed by asymmetric spacers and tilted implantation

By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.

Technique for enhancing transistor performance by transistor specific contact design

In a process strategy for forming high-k metal gate electrode structures in an early manufacturing phase, a predoped semiconductor material may be used in order to reduce the Schottky barrier between the semiconductor material and the conductive cap material of the gate electrode structures. Due to the substantially uniform material characteristics of the predoped semiconductor material, any patterning-related non-uniformities during the complex patterning process of the gate electrode structures may be reduced. The predoped semiconductor material may be used for gate electrode structures of complementary transistors.

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Markkleeberg, Germany

Uwe Griebenow