Amazon Technologies, Inc.

Advanced Micro Devices Corporation

Uwe Dannowski

Martin Thomas Pohlack

Sebastian Martin Biemueller

Nafea Bshara

Matthew Shawn Wilson

Pawel Piotr Wieczorkiewicz

Anthony Nicholas Liguori

Mark Bradley Davis

Adi Habusha

Yaniv Shapira

Stephan Diestelhorst

Thomas Friebel

David S Christie

David James Borland

Nachiketh Rao Potlapally

William John Earl

Christopher James BeSerra

Rahul Gautam Patel

Derek Del Miller

Michael P Hohmuth

Filippo Sironi

Kypros Constantinides

Bjoern Doebel

Geoffrey Plouviez

Barak Nirenberg

A computer system and associated methods are disclosed for mitigating side-channel attacks using memory page remapping. The computer system includes a main memory and a shared cache, the shared cache implementing cache set associativity determined by a portion of memory addresses of the main memory. Multiple physical memory pages are reserved for mapping to a virtual memory page, the physical memory pages differing in the respective portions of their memory addresses determining cache set associativity. Accesses to the virtual memory page result in a mapping of one of the reserved physical memory pages to the virtual memory page, with remapping events causing different ones of the physical memory pages to become mapped. This remapping results in varying cache set associativity of elements stored in the virtual memory page over time.

Obscuring memory access patterns through page remapping

A computer system and associated methods are disclosed for mitigating side-channel attacks using a shared cache. The computer system includes a host having a main memory and a shared cache. The host executes a virtual machine manager (VMM) that determines respective security keys for a plurality of co-located virtual machines (VMs). A cache controller for the shared cache includes a scrambling function that scrambles addresses of memory accesses performed by threads of the VMs according to the respective security keys. Different cache tiers may implement different scrambling functions optimized to the architecture of each cache tier. Security keys may be periodically updated to further reduce predictability of shared cache to memory address mappings.

Hardware-assisted obscuring of cache access patterns

A computer system and associated methods are disclosed for mitigating side-channel attacks using a shared cache. The computer system includes a main memory, a shared cache and a cache controller for the shared cache including a scrambling function that scrambles addresses of memory accesses according to the respective scrambling keys selected for a sequence of time periods. Different cache tiers may implement different scrambling functions optimized to the architecture of each cache tier. Scrambling keys may be updated to reduce predictability of shared cache to memory address mappings. These updates may occur opportunistically, on demand or on specified schedule. Multiple scrambling keys may be simultaneously active during transitions between active time periods.

Hardware blinding of memory access with epoch transitions

As part of a compute instance migration, a compute instance which was executing at a first server begins execution at a second server before at least some state information of the compute instance has reached the second server. In response to a determination that a particular page of state information is not present at the second server, a migration manager running at one or more offload cards of the second server causes the particular page to be transferred to the second server via a network channel set up between the offload cards of both servers, and stores the page into main memory of the second server.

Accelerated migration of compute instances using offload cards

Provided are systems and methods for enabling peer-to-peer communications between peripheral devices. In various implementations, a computing system can include a PCI switch device. The first PCI switch device can include a first port and be communicatively coupled to a first root complex port. The first PCI switch device can have access to a first PCI endpoint address range. The computing system can further include a second PCI switch device. The second PCI switch device can include a second port, connected to the first port. The second PCI switch device can be communicatively coupled to a second root complex port that is different from the first root complex port. The second PCI switch device can receive a transaction addressed to the first PCI endpoint address range, and identify the transaction as associated with the second port. The second PCI switch device can subsequently transmit the transaction using the second port.

Peer-to-peer PCI topology

Disclosed herein are techniques for migrating data from a source memory range to a destination memory while data is being written into the source memory range. An apparatus includes a control logic configured to receive a request for data migration and initiate the data migration using a direct memory access (DMA) controller, while the source memory range continues to accept write operations. The apparatus also includes a tracking logic coupled to the control logic and configured to track write operations performed to the source memory range while data is being copied from the source memory range to the destination memory. The control logic is further configured to initiate copying data associated with the tracked write operations to the destination memory.

Hardware handling memory write request during memory data migration

A computer system and associated methods are disclosed for mitigating side-channel attacks using a shared cache. The computer system includes a host having a main memory and a shared cache. The host executes a virtual machine manager (VMM) that supports a plurality of co-located virtual machines (VMs), which can initiate side-channel attacks using the shared cache. The VMM is configured to maintain respective memory maps for the VMs. The VMM is further configured to determine a subset of current host memory pages for a selected VM that can be used in a side-channel attack, relocate the contents of the current host memory pages to replacement host memory pages in the main memory, and modify the subset of entries to change current host memory pages to the respective replacement host memory pages.

Mitigating side-channel attacks via shared cache

A multi-tenant trusted platform module (MTTPM) is attached to a communication bus of a virtualization host. The MTTPM includes a plurality of per-guest-virtual-machine (per-GVM) memory location sets. In response to an indication of a first trusted computing request (TCR) associated with a first GVM of a plurality of GVMs instantiated at the virtualization host, a first memory location of a first per-GVM memory location set is accessed to generate a first response indicative of a configuration of the first GVM. In response to an indication of a second TCR associated with a second GVM, a second memory location of a second-per-GVM memory location set is accessed to generate a second response, wherein the second response is indicative of a different configuration of the second GVM.

Multi-tenant trusted platform modules

Hardware controller supporting memory page migration

A code patching component may insert a binary patch into a native-code representation of a program during execution. Prior to inserting the binary patch, a patch code analysis tool may receive a source code patch for the program, and determine that applying the source code patch would change the binary for the program outside of the patched area (e.g., due to changes in the number of lines, changes in the file names or path information for source code files from which the program is built, or line directives that embed line numbers or file names in the binary for the patched program). The tool may modify the source code patch to limit its effects to the patch area by adding empty lines, merging of lines of code, or forcing a line number change. The tool may filter line directives to match previously embedded file name information.

Limiting the effects of source code patches on corresponding native-code patches

Techniques for in-place updates of hypervisors are described herein. At a time after receiving an update hypervisor request, one or more controlling domains within a computing system invoke one or more system capabilities at least to pause execution of currently running client domains and non-essential CPUs. While the client domains and non-essential CPUs are paused, a new hypervisor in instantiated, state information is copied from the existing hypervisor to the new hypervisor. After the state and/or configuration copy is complete, control is switched form the existing hypervisor to the new hypervisor and client domains and non-essential CPUs are resumed.

In-place hypervisor updates

A method includes, in a virtualized processing system, generating a local value of a first counter. The local value is accessible while executing in a first mode of the virtualized processing system. The local value is generated based on a value of a second counter and a ratio of a rate of the first counter to a rate of the second counter. The first counter is inaccessible while executing in the first mode of the virtualized processing system and accessible while executing in a second mode of the virtualized processing system. The first mode may be a guest mode and the second mode may be a host mode. The first counter may be an ACPI Power Management Timer. The second counter may be a Time Stamp Counter.

Guest timer facility to improve management in a virtualized processing system

A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding 'WorldID.' Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding 'address space identifier' or &#x201c;ASID&#x201d;. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic. The resulting WorldID and ASID search keys are used to perform one or more TLB lookups to obtain address mapping information related to the particular address space represented by the WorldID/ASID combination.

Address mapping in virtualized processing system

A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size, the second size being greater than the first size. The mechanism further enables the operating system to use superpages including two or more contiguous pages of the first size. The size of a superpage is less than the second size. The processor further includes a page table having a separate entry for each of the pages included in each superpage. The operating system accesses each superpage using a single virtual address. The mechanism interprets a single entry in a translation lookaside buffer TLB as referring to a region of memory comprising a set of pages that correspond to a superpage in response to detecting a superpage enable indicator associated with the entry in the TLB is asserted.

Growing community of inventors

Moritzburg, Germany

Uwe Dannowski