International Business Machines Corporation

Uwe Brandt

Frank Siegfried Lehnert

Markus Helms

Thomas G Koehler

Christian Jacobi

Lisa Cranton Heller

Martin Recktenwald

Ute Gaertner

Jennifer A Navarro

Markus Kaltenbach

Thomas Köhler

Hans-Werner Tast

Willm Hinrichs

Rebecca S Wisniewski

Walter Heinrich Lipponer

Juergen Pille

Markus Buehler

Michael Billeci

Holger Wetter

Thomas Makowski

Jens Noack

Werner Juchmes

Christoph W Wandel

Thomas Kalla

Stefan Buettner

Monika Strohmer

Hans-Werner Anderson

Katherine Eve

A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.

Suspending translation look-aside buffer purge execution in a multi-processor environment

An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

Multi-engine address translation facility

Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the techniques include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. The techniques also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. The techniques include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.

Zone-SDID mapping scheme for TLB purges

A computer-implemented method includes associating an initial use order with a plurality of target sets of a translation lookaside buffer (TLB), where the initial use order indicates an order of use of the plurality of target sets. The plurality of target sets are associated with an initial least-recently-used (LRU) state based on the initial use order. A new use order for the plurality of target sets is generated. Generating the new use order includes moving a first target set to a least-recently-used position, responsive to a purge of the first target set. The LRU state of the plurality of target sets is updated based on the new use order, responsive to the purge of the first target set. The first target set is identified as eligible for replacement according to an LRU replacement policy of the TLB, based at least in part on the purge of the first target set.

Incorporating purge history into least-recently-used states of a translation lookaside buffer

Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the embodiments include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. Embodiments also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. Embodiments include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.

Disclosed herein is a method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.

The present disclosure relates to a method of operating a hierarchical translation lookaside buffer (TLB). The TLB comprises at least two TLB levels, wherein a given entry of the upper level TLB comprises a portion of bits for indicating related entries in the lower level TLB. The method comprises the following when a TLB miss is encountered for a requested first virtual address. A first table walk is performed to obtain the absolute memory address for the first virtual address. A logical tag is stored. The logical tag comprises the portion of bits that has been identified in association with the first table walk. In response to determining that a concurrent second table walk, of the ongoing first table walk, that has a second virtual address that addresses the same entry in the upper level TLB as the first virtual address is writing in the TLB, the stored logical tag may be incremented. And, the incremented logical tag and the obtained absolute memory address may be stored in the TLB.

Link consistency in a hierarchical TLB with concurrent table walks

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Stuttgart, Germany

Uwe Brandt