Infineon Technologies Flash Gmbh & Co. Kg

Qimonda Flash Gmbh & Co. Kg

Uwe Augustin

Konrad Seidel

Detlev Richter

Andreas Kux

Mirko Reissmann

Gert Koebernick

Volker Zipprich-Rasch

Hans Heitzer

Daniel-André Löhr

Sören Irmer

Gert Kobernik

Gert Köbernik

A method is provided for programming a block of memory cells of a non-volatile memory device. A first group of memory cells of the block of memory cells is selected. At least one programming pulse is programmed into all memory cells of the first group. A threshold level is detected for each one of the memory cells of the first group only. The first group of memory cells is verified by comparing each one of the detected threshold levels with predefined target levels provided for each one of the first group of memory cells.

Method for programming a block of memory cells, non-volatile memory device and memory card device

A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.

Memory device with adaptive sense unit and method of reading a cell array

A memory device () includes a memory array (). The memory array () has at least one memory area () that includes a plurality of conductive lines () and a plurality of memory cells () connected to the conductive lines (). The conductive lines () are arranged at positions (n) within the memory area (). The memory cells () are erasable and are programmable by application of an electrical programming pulse (P) supplied via a respective conductive line (). The memory device () is constructed such that for programming of a memory cell () an electrical programming pulse (P) is applied which has a programming pulse profile (PP) depending on the position (n) of a respective conductive line () to which the memory cell () is connected.

Memory device and method for operating a memory device

A method for determining a reading voltage for reading data out of a non-volatile semiconductor memory, wherein the semiconductor memory comprises a plurality of memory cells grouped in a first memory area and a second memory area. A given number of '0's are stored into the second memory area, and an equal number of '0's and &#x201c;1&#x201d;s are stored in the memory cells of the first memory area. The memory cells of the first memory area are read using an initial first reading voltage. The first reading voltage is adjusted and the memory cells of the first memory area are re-read until an equal number of &#x201c;0&#x201d;s and &#x201c;1&#x201d;s are read out of the memory cells of the first memory area, to thereby obtain a final first reading voltage. An initial second reading voltage is determined on the basis of the final first reading voltage. The memory cells of the second memory area are read using the initial second reading voltage. The second reading voltage is adjusted and the memory cells of the second memory area are re-read until the number of &#x201c;0&#x201d;s read is equal to the number of &#x201c;0&#x201d;s stored in the second memory area, thereby obtaining a final second reading voltage. The final second reading voltage is used as a reading voltage for reading the memory cells of the semiconductor memory.

Non-volatile semiconductor memory

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Dresden, Germany

Uwe Augustin