Macronix International Co., Ltd.

Uway Tseng

Wenpin Lu

Hung-Yu Chiu

Kent Kuohua Chang

Ching-Yu Chang

Chun-Lien Su

Ming-Shang Chen

Wen-Pin Lu

Jung-Yu Hsieh

A method is provided for forming a non-volatile memory device. The method includes forming a stacked structure including a tunnel oxide layer, a floating gate, a thin oxide layer, and a control gate on a semiconductor substrate. Etching is used to define the sidewalls of the stacked structure. Dopants are implanted into exposed areas of the substrate to form source and drain regions within the substrate adjacent to the stacked structure. A liner dielectric layer is formed on the sidewalls of the stacked structure to patch the etching damage. Thereafter, a nitride barrier layer is formed on the liner dielectric layer, and an oxide spacer is formed on the nitride barrier layer. The nitride barrier layer can trap negative charge and thus act as a relatively high barrier at the tunneling oxide edge. Therefore, the threshold voltage difference between the initial erase of the memory device and the erase after many cycles is reduced.

Non-volatile memory device having a nitride barrier to reduce the fast erase effect

A method of forming a memory device having a self-aligned contact is described. The method includes providing a substrate having a floating gate dielectric layer formed thereon, forming a floating poly gate layer on the floating gate dielectric layer, forming a first silicon nitride layer on the floating poly gate layer, and forming a patterned photoresist layer on the first silicon nitride layer. The method further includes etching the first silicon nitride layer and the floating poly gate layer using the patterned photoresist layer as an etch mask, forming an oxide layer over the exposed etched areas, removing the patterned photoresist layer and the first silicon nitride layer to expose the floating poly gate layer, forming poly spaces in the floating poly gate layer, and depositing a second silicon nitride layer over the poly spaces of the floating poly gate layer to form a self-aligned contact.

Method of fabricating a memory device having a self-aligned contact

A method of reducing charge loss for nonvolatile memory. First, a semiconductor substrate having a semiconductor device thereon is provided. Next, a dielectric layer is formed on the entire surface of the semiconductor substrate, and a thermal treatment is performed in an atmosphere containing a reactive gas, and the reactive gas reacts with free ions remaining on the semiconductor substrate from prior manufacturing processes. Finally, a metal layer is formed on the dielectric layer.

Method of reducing charge loss for nonvolatile memory

A fabrication method for a cobalt-salicide contact is described. A deep sub-micron contact opening is formed on a substrate. A silicon nitride spacer is further formed on the contact sidewall. A cobalt layer is further deposited in the contact opening, followed by sequentially forming an ionized metal plasma titanium layer and a chemical vapor deposited titanium nitride layer. A first rapid thermal process is performed and a wet etching is performed to remove the titanium/titanium nitride layer. A second rapid thermal process is performed, followed by filling the contact opening with a conductive layer.

Method for fabricating cobalt salicide contact

A memory device is formed on a silicon substrate. A blocking layer is thereafter formed to cover a stacked gate of the memory device. A gettering layer is formed on the blocking layer followed by planarizing of the gettering layer to a predetermined thickness. A first barrier layer is then formed on the gettering layer. A contact hole is formed to penetrate through the first barrier layer, the gettering layer and the blocking layer down to the surface of the memory device. Following that, a second barrier layer is created to cover the first barrier layer and the contact hole. Finally, portions of the second barrier layer are etched back to make a barrier spacer on the side wall of the contact hole. Therein, the first barrier layer and the barrier spacer prevent mobile atoms from vertically diffusing and laterally diffusing, respectively, into the memory device.

Method of fabricating a non-volatile memory device to eliminate charge loss

The invention provides a method for forming a semiconductor gate, by forming spacers to isolate the interface between the HDP dielectric layer and the polysilicon gate being exposed, thereby preventing single bit failure resulting from defects at the interface between the HDP dielectric layer and the polysilicon gate. After a cap layer is formed on a conductive structure over the substrate, a HDP dielectric layer is formed exposing the cap layer. A top of the HDP dielectric layer is higher than a top of the first conductive layer. After removing the cap layer to form a recess between the HDP dielectric layer and on the conductive structure, spacers are formed on sidewalls of the recess. Afterwards, a conductive layer is formed and connected to the conductive structure.

Method for forming gate

The present invention fabricates an oxide-nitride-oxide (ONO) layer of an NROM. A first oxide layer is formed on the surface of the substrate of a semiconductor wafer. Then two CVD processes are performed to respectively form a first nitride layer and a second nitride layer on the surface of the first oxide layer, and the boundary between the second nitride layer and the first nitride layer is so forming an interface. Thereafter, a second oxide layer is formed on the surface of the second nitride layer completing the process of manufacturing the ONO layer. The second nitride layer and the first nitride layer are used as a floating gate of the NROM, and the interface is used as a deep charge trapping center to improve the charge trapping efficiency, and furthermore, to improve the endurance and reliability of the NROM.

Method for fabricating an ONO layer of an NROM

A method for forming a low loss dielectric layer in the tungsten chemical mechanic grinding process is disclosed. After forming a dielectric layer on the semiconductor substrate and smoothing the dielectric layer as an inner dielectric layer, a stop layer of undoped silicon dioxide, organ spin on glass, or silicon oxygen nitride are coated thereon. After process of plug lithographic and etching, a barrier layer of tungsten plug and metal tungsten are deposited sequentially. Finally, the surplus tungsten metal layer on the surface of a dielectric layer is removed by chemical mechanic grinding process until the stop layer is exposed. In the present invention, the stop layer is used to repair the scratches or defects generated from the smoothness in the chemical mechanic grinding process. Furthermore, in the tungsten chemical mechanic grinding process, it can assure that the inner dielectric layer will not be ground so that the object of low loss is achieved.

Method for forming a low loss dielectric layer in the tungsten chemical mechanic grinding process

A method of gettering layer for improving chemical mechanical polishing process in flash-memory production is provided to protect a memory element against baking and keep its reliability by blockading mobile electrons with the gettering layer. Moreover, by taking advantage of the gettering layer, reduction of the thickness of the ILD for increasing the etching margin, the deposition margin, and the remaining margin of oxides are made possible.

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Hsinchu, Taiwan

Uway Tseng