International Business Machines Corporation

Microelectronics and Computer Technology Corporation

Other

Uttam Shyamalindu Ghoshal

David A Gibson

Harry Kroger

Sang Hoo Dhong

Joel Abraham Silberman

Osamu Takahashi

Curtis Nathan Potter

Snigdha Ghoshal

Errol Wayne Robinson

Apparatus and method for sub-ambient cooling using thermoelectric dynamics in conjunction with novel configuration schemes to maximize energy transport to thereby increase the efficiency of thermoelectric cooling. In one form, a junction maximizes energy transport being positioned between and coupled to thermoelectric elements having minimal spacing to provide efficient thermoelectric cooling. Preferable implementations provide thermoelectric elements configured such that thermal energy is transferred away from the junction and dissipated by thermal sinks coupled to thermoelectric elements

Thermoelectric cooling apparatus and method for maximizing energy transport

Apparatus, method, and signal for sub-ambient cooling using thermoelectric dynamics in conjunction with configurations and activation schemes to maximize the mean time between failure (MTBF) of thermoelectric coolers. In one form, a signal is provided which periodically alters the state of the Peltier devices from an active state to a passive state. During the active state the Peltier device provides maximum cooling and during the passive state the Peltier device minimizes thermal leakage while reducing cooling. Preferable implementations provide multiple signals to thermoelectric arrays such that, for a predetermined time, a first set of the arrays are in the active state while a second set of the arrays are in the passive state to thereby minimize failures and maximize the MTBF of the thermoelectric arrays.

Highly reliable thermoelectric cooling apparatus and method

Thermoelectric cooler for providing sub-ambient cooling and method of fabricating same. In one form, sub-micron thermoelectric coolers are formed using doped thin films as thermoelectric elements. The thin film thermoelectric elements are created on thermally and electrical isolating materials using an electrochemical deposition process with a junction formed between the thermoelectric elements. The sub-micron thermoelectric coolers can then be used to locally cool nanoscopic geometric regions such as regions of an integrated circuit or can be configured in an array for large scale microscopic cooling applications.

Nanoscopic thermoelectric coolers

Thermoelectric cooler for providing sub-ambient cooling to an object and method of fabricating same. In one form, the thermally conducting but electrically insulating substrate interfaces used in conventional thermoelectric coolers are replaced by ultra-thin semiconductor substrates having a plurality of doped regions. Diodes formed in the semiconductor substrates are maintained in a reverse biased state to provide the desired electrical isolation necessary for operating the thermoelectric coolers. The reverse biased state is maintained by either the inherent properties resulting from forming the diode in the semiconductor material or through application of a bias voltage to the semiconductor substrates though a layer of conductive material deposited on the outermost surfaces of the substrates.

Electrically-isolated ultra-thin substrates for thermoelectric coolers

A method for fabricating a transistor having a variable threshold voltage is disclosed. Energy levels of a transistor can be represented by a valance band, a conduction band, and a Fermi level. In order to fabricate a transistor with a variable threshold voltage, a region of the transistor is initially doped with a first dopant having a first energy level below the Fermi level. The region of the transistor is subsequently doped with a second dopant having a second energy level above the Fermi level. Alternatively, the region of the transistor can be initially doped with a first dopant having a first energy level above the Fermi level, and then the region of the transistor can be subsequently doped with a second dopant having a second energy level below the Fermi level.

Method for fabricating a transistor having a variable threshold voltage

A system for synchronizing circuit operation within an integrated circuit having a high frequency clock is disclosed. The system includes an oscillator for providing a clock signal, and a clock signal complement. A two conductor transmission line is utilized to distribute the clock signal. The two conductor transmission line has a first conductor coupled to the clock signal and a second conductor coupled to the clock signal complement provides sub-circuits within the integrated circuit with a differential clock signal. Negative impedance transmission line terminations are then attached in parallel with the transmission line. The terminations boost the clock signal transition times and the clock signal complement transition times to provide high frequency circuit synchronization within the integrated circuit.

High frequency clock signal distribution utilizing CMOS negative impedance terminations

A method of fabricating an integrated circuit having air-gaps between interconnect levels. In a preferred embodiment, an integrated circuit is partially fabricated. The partially fabricated integrated circuit includes a top layer, interconnect structures having a cladding layer, dielectric layers and an etch stop layer resistant to certain first types of etchants. The top layer of the integrated circuit is etched with a second type of etchant. The dielectric layers are then etched with one of the first types of etchants until the etch stop layer is reached. Thus, portions of the interconnect structures are exposed to create interconnect islands surrounded by air. A cover is mechanically placed over the exposed interconnect islands to protect the integrated circuit from dust particles.

Practical air dielectric interconnections by post-processing standard CMOS wafers

A method for performing a high-temperature burn-in test on integrated circuits is disclosed. A thin-film is placed on top of an integrated circuit having multiple transistors. An infra-red filter is then placed on top of the thin-film. All the transistors of the integrated circuit are radiated by an infra-red source through the thin-film and the infra-red filter when a high-temperature burn-in test is being performed.

Method for performing a high-temperature burn-in test on integrated circuits

A thermoelectric cooling apparatus which includes a Peltier device or a thermoelectric element coupled to a hot source and a cold sink. The hot source dissipates heat produced by the thermoelectric element. The cold sink is coupled to a mass to be cooled. A means for supplying power to the thermoelectric element is provided and a means for selectively thermally coupling the thermoelectric element to the hot source is provided. Selectively thermally switching the thermoelectric element to the hot source allows heat to be dissipated to the hot source when the thermoelectric element possesses excess heat. Dissipating the excess heat when the excess heat is present allows higher efficiencies to be attained in thermoelectric cooling.

Enhanced duty cycle design for micro thermoelectromechanical coolers

A digitally adjustable inductive element which can be implemented in an integrated circuit. The digitally adjustable inductive element can include a first inductor, and a digital inductance controller operatively coupled to the first inductor which can be utilized to vary the effective inductance of the first inductor. The digitally adjustable inductive element can include a second inductor operatively coupled to the first inductor, and a digital current controller operatively coupled to the second inductor. The digital current controller can include a number of transistors operatively coupled to the second inductor. The digitally adjustable inductive element can be utilized to create a tunable oscillator. The tunable oscillator can include a first inductor, a digital inductance controller operatively coupled to the first inductor which can be utilized to vary the effective inductance of the first inductor, and an oscillator circuit which generates an oscillating signal utilizing the effective inductance of the first inductor. The tunable oscillator can include a second inductor operatively coupled to the first inductor, and a digital current controller operatively coupled to the second inductor. The digital current controller can include a number of transistors operatively coupled to the second inductor.

Digitally adjustable inductive element adaptable to frequency tune an LC

A system for measuring magnetic fields produced by an integrated circuit device-under-test includes a clock generator configured to generate a clock signal, a delay circuit configured to generate a delayed clock signal having a known delay relative to the clock signal, a pulse generator configured to generate a series of pulses having a frequency corresponding to a frequency of the clock signal, the pulses of the series of pulses being offset from the clock signal by the known delay, and a sensor having a property that varies in response to a magnetic field at the sensor. A sampling circuit connected to the sensor and to the pulse generator is configured to measure the property of the sensor at times corresponding to pulses of the series of pulses, and to produce a sampling signal having, for each pulse, a first value (e.g., a logical one) when the property of the sensor indicates that the magnetic field at the sensor exceeds a threshold amount and a second value (e.g., a logical zero) when the property of the sensor indicates that the magnetic field at the sensor does not exceed the threshold amount. A digital filter is connected to the sampling circuit and configured to produce a first indicator when a number of first values in the sampling signal exceeds a predetermined amount and to produce a second indicator when a number of first values in the sampling signal does not exceed a predetermined amount. A counter connected to the digital filter is configured to increment an output signal in response to one of the first and second indicators and to decrement the output signal in response the other of the first and second indicators. A feedback loop including a digital-to-analog converter is connected to the counter and configured to produce an electrical signal proportional to the output signal, the electrical signal causing the feedback loop to produce a feedback magnetic field in proportion to the output signal, the feedback magnetic field being a component of the magnetic field at the sensor. The output signal of the counter corresponds to a magnetic field produced by the device-under-test.

High speed magnetic flux sampling

A thermoelectric cooling (TEC) device is thermally coupled, in close proximity, to a GMR head chip. When power is applied to the TEC device, heat is extracted from the GMR head chip by heat transfer to the cold end of the TEC device and rejected by heat pipes or cooling fins along the slider arm, in one embodiment. In another embodiment, a TEC device is integrated with the GMR head chip such that the cold end of the TEC device is physically and thermally coupled with the GMR head chip. Heat is transferred from the GMR head chip to a thermal spreader pad on the `hot` end of the integrated GMR/TEC device.

Method and apparatus for cooling GMR heads for magnetic hard disks

A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, a discharger transistor, several input transistors, and an invertor. Connected to a power supply, the precharge transistor receives a first clock input. The discharge transistor, connected to the ground, receives a second clock input. The input transistors is coupled between the precharge transistor and the discharge transistor. Each of the input transistors receives a signal input. The inverter has an input coupled to the precharge transistor, and an output to yield a signal output. The inverter includes a first transistor and a second transistor connected in series, and the output of the inverter is connected to a body of the first transistor.

Domino logic circuit having a clocked precharge

A highly efficient current controlled thermoelectric cooling system is disclosed. The highly efficient current controlled thermoelectric cooling system includes a first thermal sink, a second thermal sink, a thermoelectric element, and a variable current source. The first thermal sink has a temperature higher than an ambient temperature while the second thermal sink has a temperature lower than the ambient temperature. The first thermal sink is continuously coupled to the thermoelectric element while the second thermal sink is selectively coupled to the thermoelectric element via a mass. A variable current source provides a controlled current pulse to the thermoelectric element such that heat transfer can be effectively achieved between the thermoelectric element and both thermal sinks.

Thermoelectric cooling system

A solid state thermal switch providing thermal conductivity in an ON state and enhanced thermal isolation in an OFF state. The thermal switch is manufactured on a substrate by forming an oxide layer under a thin semiconducting layer. The thin semiconducting layer can be made from silicon or a silicon germanium lattice structure. The thin silicon layer is cracked by a neutron bombardment process. A drain and a source are then etched into the thin silicon layer. Cracks in the thin silicon layer disrupt quiescent thermal conductivity in the electron transport layer between the gate and source when the solid state thermal switch is in the OFF state. The thin semiconducting layer transports electrons and heat when the solid state thermal switch is in the ON state. The cracks created in the silicon layer provide thermal isolation from the drain to the source when the thermal switch is in an OFF state and allow heat conduction when the solid state thermal device is in the ON state.

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Austin, TX, United States of America

Uttam Shyamalindu Ghoshal