Cadence Design Systems, Inc.

Utpal Bhattacharyya

Amit Kumar Sharma

Taranjit Singh Kukal

Randall Scott Lawson

Steven Roberts Durrill

Edward Brian Acheson

Robert Roesler

The present disclosure relates to a system and method for use in an electronic circuit design. Embodiments may include receiving, using a processor, one or more DFM rules files from at least one PCB fabricator and importing the one or more DFM rules files to a DFM rule aggregator database. Embodiments may also include grouping one or more rules associated with the one or more DFM rules files using an automated or manual operation. Embodiments may further include performing automatic or manual rule aggregation on the grouped rules based upon, at least in part, rules aggregation information including a DFM template file.

System and method for consolidating and applying manufacturing constraints

The present disclosure relates to a system and method for use in an electronic circuit design. Embodiments may include an electronic computer aided design ('CAD') system configured to receive one or more design rules and to receive one or more manufacturing rules. The CAD system may be further configured to analyze design database objects from the electronic design with respect to the manufacturing rules. The CAD system may generate a manufacturing output file, based upon, at least in part, the analyzing. Embodiments may also include a signoff computer aided manufacturing ('CAM') station configured to receive the manufacturing output file. The CAM station may be configured to attempt to validate the manufacturing output file.

Process for analyzing printed circuit board and packaging manufacturing design rules

Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.

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Noida, India

Utpal Bhattacharyya