Nvidia Corporation

Intel Corporation

Qualcomm Incorporated

Utpal Barman

Edward L Riegelsberger

Jyotirmaya Swain

Uday Ramakrishna Naik

Nakul Manjunath

Adarsh Kalliat

Subramanya N N

Raji Cherian

Subhayu Basu

A subordinate device includes a local clock and a protocol controller. The protocol controller is coupled to a bus that includes a data wire. The protocol controller is configured to receive, on the data wire from a principal device, a read command addressed to the subordinate device indicating initiation of a read transaction. The protocol controller is also configured to, after a delay window, send synchronization pulses to the principal device based on the local clock, where a duration of the delay window is greater than a clock cycle of the local clock. The protocol controller is further configured to, after sending the synchronization pulses, send data on the data wire to the principal device based on the local clock during the read transaction.

Read synchronization delay at subordinate device for 1 wire protocol

According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge ('first edge') of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.

Programmable delay circuit providing for a wide span of delays

Read leveling of memory units designed to receive access requests in a sequential chained topology writing a data pattern to the memory array. In an embodiment, a memory controller first writes a desired pattern into the memory array of a memory unit and then iteratively determines the accurate calibrated delay by setting a compensation delay to a test value, reading a data portion from the memory array based on the test value for the compensation delay, comparing the data portion with an expected data, determining that the test value is a calibrated compensation delay for the memory unit if the data portion equals the expected value.

Read leveling of memory units designed to receive access requests in a sequential chained topology

A memory controller provided according to an aspect of the present invention uses a slower clock signal during write leveling compared to when performing write operations thereafter. Due to such use of a slower clock signal, the various desired delays can be determined accurately and/or easily. In an embodiment, the frequency of the slower clock signal is determined based on the maximum fly-by delay (generally the delay between sending of a signal on the shared sequential path and the receipt at the memory unit in the sequence) that may be present in the memory system. For example, if the fly by delay can be M (an integer) times the time period of the clock signal during normal write operations, the slower clock signal may have a time period of M times that of the clock signal during write operation.

Write leveling of memory units designed to receive access requests in a sequential chained topology

Techniques that may be utilized in a multiprocessor computing system are described. In one embodiment, one or more addresses (such as source and/or destination addresses) of a received packet are encoded to reduce the size of the addresses and the encoded one or more addresses are utilized to classifying the received packet.

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Bengaluru, India

Utpal Barman