Apple Inc.

Utku Seckin

Long Kong

Feng Zhao

Simone Gambini

Hanwen Yang

Shinan Lu

Joachim S Hammerschmidt

Robert G Lorenz

Benjamin W Cook

Chia-Hsiang Chen

Christian Venerus

Tao Mai

Michael D Scott

Chia-hsiang Chen

Vikram Magoon

The present disclosure relates to compensating for temperature variation of a mixer. Embodiments herein may include the mixer, a calibration circuit coupled to the mixer, a replica mixer circuit coupled to the calibration circuit, and a temperature compensation circuit coupled to the calibration circuit. The replica mixer circuit may generate or be used to generate a reference voltage that varies with a common mode voltage and/or a threshold voltage of a replica mixer. The reference voltage may be applied to a resistor ladder of the calibration circuit to adjust a bias voltage and compensate for temperature variations. Further, the temperature compensation circuit may generate a temperature coefficient that may be applied to a current going through the calibration circuit to facilitate compensating for temperature variation.

Mixer second-order input-intercept point temperature compensation

The present disclosure relates to compensating for temperature variation of a mixer. Embodiments herein may include performing a single-point Fast Fourier Transform (FFT) (or complex downconversion with DC average) for a number of samples to obtain a transform for each of the number of samples, phase aligning a set of phases associated with each transform, and averaging each transform to generate an analog-to-digital converter (ADC) power value. Further, the disclosed embodiments may include generating a compensation value based on the analog-to-digital converter power value and applying the compensation value to the calibration circuit of the mixer to compensate for a second-order intermodulation product.

A signal transmitter may include a waveform synthesis circuit and a signal transmission circuit. The waveform synthesis circuit may store values of a reference waveform for a selected channel of the signal transmitter, and use the stored values to generate values of reference waveforms for one or more other channels of the signal transmitter. The waveform synthesis circuit may further include a sampling boost circuit to generate one or more additional values for the reference waveforms. The waveform transmission circuit may generate signals for the channels of the signal transmitter based at least in part on the values of the reference waveforms, and transmit the signals via one or more antennas.

Signal transmitters with size-reduced on-chip memory

This disclosure is directed to a transmitter including a phase locked loop (PLL), a modulator, and a power amplifier (PA). A controller including programmable and/or hardened logic circuitry may be coupled to the PLL and the modulator. The controller may provide encoded signals based on quadrature phase shift keying (QPSK) scheme for transmission by the transmitter. In particular, the controller may provide multiple bursts of pulses indicative of data packets to the modulator. Moreover, the controller may provide instructions indicative of generating clock signals with in-phase and quadrature phases to the PLL. The PLL may generate clock signals corresponding to the in-phase and quadrature phases. As such, the transmitter may generate in-phase and quadrature output signals based on receiving each burst of pulses with either in-phase or quadrature phases.

Wireless transmitter with improved data rate

An electronic device may include wireless circuitry with a baseband processor, a transceiver, a front-end module, and an antenna. The transceiver may include mixer circuitry. The mixer circuitry may include switches controlled by oscillator signals. The mixer circuitry may also include oscillator phase noise cancelling capacitors controlled by inverted oscillator signals. Operated in this way, the mixer circuitry exhibits improved noise figure performance.

Mixer circuitry with noise cancellation

A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal.

Digital power amplifier with RF sampling rate and wide tuning range

A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.

Digital filter with programmable impulse response for direct amplitude modulation at radio frequency

A non-integer divider for dividing the frequency of a signal is disclosed. A non-integer divider includes a first divider that divides the frequency of a first signal. A mixer is coupled to receive the first signal, and a second signal having a frequency equivalent to that output by the first divider. The mixer outputs a third signal having a frequency based on respective frequencies of the first and second signal. A second divider receives and frequency divides the third signal to produce a fourth signal. A ratio of the frequency of the first signal to the fourth signal is a non-integer value.

Non-integer frequency divider

Various embodiments of a segmented R-DAC are disclosed. In one embodiment, a segmented R-DAC includes first and second DACs arranged to receive most and least significant bits, respectively. The segmented R-DAC also includes a first capacitor coupled between an output of the first DAC and an output of the second DAC, and a second capacitor coupled between the output of the second DAC and a ground node. The capacitance of the second capacitor has a value that is a predetermined multiple of the capacitance value of the first capacitor.

Linearity improvement for segmented R-DACs

A supply modulator for a polar power amplifier and method for operating the same are disclosed. An apparatus includes an amplifier having an input for receiving a phase modulated (PM) signal. A modulator is arranged to receive an amplitude modulated (AM) signal and provide a supply voltage to the amplifier, the supply voltage varying based on the AM signal. A detector circuit may detect the supply voltage exceeding a first threshold or falling below a second threshold. The detector circuit includes a current source arranged to provide a bias current to the modulator. When the supply voltage exceeds the first threshold, the detector causes an increase in the bias current provided to the modulator. Similarly, when the supply voltage falls below a second threshold, the detector causes an increase of the bias current supplied to the modulator.

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Santa Clara, CA, United States of America

Utku Seckin