International Business Machines Corporation

Ute Gaertner

Lisa Cranton Heller

Erwin F Pfeffer

Jennifer A Navarro

Frank Siegfried Lehnert

Angel Nunez Mencias

Jakob Christopher Lang

Christine Axnix

Timothy John Slegel

Rebecca S Wisniewski

Markus Helms

Uwe Brandt

Thomas G Koehler

Christian Jacobi

Joerg Deutschle

Michael F Fee

Norbert Hagspiel

Thomas Köhler

Damian Leo Osisek

Klaus J Getzlaff

Bruce A Wagar

Christoph Raisch

Elpida Tzortzatos

Khary J Alexander

Bruce C Giamei

Hans-Werner Tast

Jonathan T Hsieh

Kerstin Claudia Schelm

Christian Borntraeger

Hanno Ulrich

Christine M Yost

Christopher S Smith

Harald Boehm

Chung-Lung K Shum

Dan F Greiner

Donald W Schmidt

Martin Recktenwald

Aaron Tsai

Jane Helen Bartik

Wilhelm Ernst Haller

Timothy J Siegel

Matthias Fertig

Gregory Miaskovsky

Gunter Gerwig

John D MacDougall

Klaus J&ouml;rg Getzlaff

Oliver Laub

Klaus-Joerg Getzlaff

An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.

Reset dynamic address translation protection instruction

Operating system deactivation of write protection for a storage block is provided absent quiescing of processors in a multi-processor computing environment. The process includes receiving an address translation protection exception interrupt resulting from an attempted write access by a processor to a storage block, and determining by the operating system whether write protection for the storage block is active. Based on write protection for the storage block not being active, the operating system issues an instruction to clear or modify translation lookaside buffer entries of the processor associated with the storage block, absent waiting for an action by another processor of multiple processors of the computing environment, to facilitate write access to the storage block proceeding at the processor.

Operating system deactivation of storage block write protection absent quiescing of processors

A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.

Suspending translation look-aside buffer purge execution in a multi-processor environment

Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the techniques include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. The techniques also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. The techniques include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.

Zone-SDID mapping scheme for TLB purges

Data collection is facilitated by a multi-threaded processor. One thread of the processor obtains data placed in a buffer by another thread of the processor. The thread placing the data in the buffer is an execution thread executing a customer application and the one thread obtaining the data from the buffer is an assist thread. The assist thread stores the data obtained from the buffer in a selected location, such as a cache, main memory, a measurement control block, a persistent storage device or a network.

Data collection in a multi-threaded processor

A cache structure implemented in a microprocessor core include a set predictor and a logical directory. The set predictor contains a plurality of predictor data sets containing cache line information, and outputs a first set-ID indicative of an individual predictor data set. The logical directory contains a plurality of logical data sets containing cache line information. The cache structure selectively operates in a first mode such that the logical directory receives the first set-ID that points to an individual logical data set, and a second mode such that the logical directory receives a currently issued micro operational instruction (micro-op) containing a second set-ID that points to an individual logical data set. The logical directory performs a cache lookup based on the first set-ID in response to operating in the first mode, and performs a cache lookup based on the second set-ID in response to operating in the second mode.

Cache directory that determines current state of a translation in a microprocessor core cache

Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the embodiments include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. Embodiments also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. Embodiments include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.

Disclosed herein is a method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.

Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.

Quiesce handling in multithreaded environments

A method includes generating a set of virtual-machine-specific (VMS) encryption keys for a dedicated virtual machine, storing the set of VMS encryption keys in a protected memory, storing a first look-up table in the protected memory, and replacing an encryption key stored in a crypto unit with at least one VMS encryption key of the set of VMS encryption keys in an operation mode where the dedicated virtual machine is executed by a processor. The protected memory is selectively excluded from access by operating systems executable on a computer system. The look-up table being accessible only by firmware of the computer system.

Protecting a memory from unauthorized access

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Schoenaich, Germany

Ute Gaertner