Globalfoundries Singapore Pte. Ltd.

Ushasree Katakamsetty

Chiu Wing Hui

Wee Kwong Yeo

Valerio Perez

Shyue Fong Quek

Edward Kah Ching Teoh

Yang Qing

Enhancements in lithography for forming an integrated circuit are disclosed. The enhancements include a topography analysis of a design data file to obtain accumulative topography information for different mask levels. The topography information facilitates topography driven optical proximity correction and topography driven lithography.

Topography driven OPC and lithography flow

A design or lithographic enhancement process, a method for forming a device based on the lithographic enhancement process and a system for pattern enhancement are presented. The process includes processing a design data file. The design data file includes information of design layers in an integrated circuit (IC). Processing the design data file includes analyzing the design data file and patterns in the design data file are enhanced taken into consideration topography information of design layers corresponding to masks of the IC.

Surface topography enhanced pattern (STEP) matching

A method for selecting and placing of an IP block in a SOC design based on a topology and/or a density of the SOC design is disclosed. Embodiments include: displaying a user interface; causing, at least in part, a presentation in the user interface of a topology and density view of a SOC design that includes an IP block; and modifying, prior to a tape-out of the SOC design, topology and/or density transition for the IP block in the SOC design based on the presentation.

Growing community of inventors

Singapore, Singapore

Ushasree Katakamsetty