Advanced Micro Devices Corporation

Globalfoundries Inc.

Advance Micro Devices, Inc.

Ursula Q Quinto

Bharath Rangarajan

Bhanwar Singh

Ramkumar Subramanian

Khoi A Phan

Michael K Templeton

Fei Wang

Jeffrey Allan Shields

George Jonathan Kluth

Kathleen R Early

Michael T Templeton

The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.

Recirculation and reuse of dummy dispensed resist

Re-circulation and reuse of dummy-dispensed resist

An edge bead removal system and method is provided that employs a nozzle for applying edge bead removal solvent to an edge bead of a photoresist material layer disposed on a wafer. The nozzle includes a liquid chamber that can be connected to a supply of edge bead removal and an air supply chamber that can be connected to a supply of air. The supply of air is isolated from the liquid supply chamber during application of the edge bead removal solvent and communicates via the air supply chamber to the liquid supply chamber after application of the edge bead removal solvent thus removing any droplets of edge bead removal solvent remaining in the nozzle tip. A system is also provided that includes an absorbent material that moves from a rest position, during application of the edge bead removal solvent, to an absorbing position that removes or catches any droplets of edge bead removal solvent remaining on the nozzle tip after application of the edge bead removal solvent is completed. A nozzle is also provided that includes a liquid supply chamber with an inner cylindrical surface that is made of or coated with either a hydrophobic material and/or a hydrophilic material.

Low defect EBR nozzle

One aspect of the present invention relates to a method of forming trench isolation regions within a semiconductor substrate, involving the steps of forming trenches in the semiconductor substrate; depositing a semi-conformal dielectric material over the substrate, wherein the semi-conformal dielectric material has valleys positioned over the trenches; forming an inorganic conformal film over the semi-conformal dielectric material; polishing the semiconductor substrate whereby a first portion of the inorganic conformal film is removed thereby exposing a portion of the semi-conformal dielectric material, and a second portion remains over the valleys of the semi-conformal dielectric material; removing the exposed portions of the semi-conformal dielectric material; and planarizing the substrate to provide the semiconductor substrate having trenches with a dielectric material therein.

Self-aligned/maskless reverse etch process using an inorganic film

A method of manufacturing an integrated circuit which reduces damage to the underlying base layer and the created oxide structures is disclosed herein. The method includes providing a hybrid stack disposed over an underlying layer, providing an IC structure pattern over the hybrid stack, selectively removing the top layer and a portion of the bottom layer according to the IC structure pattern, leaving a protective portion of the bottom layer according to the IC structure pattern, removing the protective portion of the bottom layer, building oxide structures in the underlying layer according to the IC structure pattern, and removing remaining portions of the hybrid stack. An integrated circuit is also disclosed which is prepared by a process including: providing a hybrid stack disposed over an underlying layer, providing an IC structure pattern over the hybrid stack, selectively removing a portion of the hybrid stack according to the IC structure pattern, leaving a protective portion of the bottom layer according to the IC structure pattern, building oxide structures on the underlying layer, and removing remaining portions of the hybrid stack.

Hybrid stack method for patterning source/drain areas

In one embodiment, the present invention relates to a method of treating a patterned resist involving providing the patterned resist having a first number of structural features, the patterned resist comprising an acid catalyzed polymer; contacting a coating containing a coating material, at least one basic compound, a photoacid generator, and a dye with the patterned resist; irradiating the coated patterned resist; permitting a deprotection region to form within an inner portion of the patterned resist; and removing the coating and the deprotection region to provide a second number of patterned resist structural features, wherein the first number is smaller than the second number.

Chemical feature doubling process

The present invention relates to a system for mitigating wafer disformation. The system includes at least a first polishing pad and a second polishing pad for polishing a wafer surface. A CMP drive system selectively applys the first and second polishing pads against the wafer surface at first and second pressures, respectively. A measuring system measures a wafer surface thickness associated with a first circumferential region of the wafer polished by the first polishing pad and a wafer surface thickness associated with a second circumferential region of the wafer polished by the second polishing pad. A processor employs information from the measuring system to control the CMP drive system.

System and method for mitigating wafer surface disformation during chemical mechanical polishing (CMP)

A process for fabricating a memory cell, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with an n-type dopant, wherein the resist mask is used as an ion implant mask, and etching the resist mask upon implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the etching of the resist mask includes performing a blanket anisotropic etch to reduce the thickness of the resist mask and round the edges of the resist mask. Preferably, the blanket anisotropic etch is performed using an etch including an element selected from the group consisting of nitrogen, hydrogen, chlorine, and helium.

Use of an etch to reduce the thickness and around the edges of a resist mask during the creation of a memory cell

A reverse lithographic process is provided for more densely packing semiconductors onto a semiconductor wafer. A semiconductor wafer having deposited a number of layers of semiconductor materials has a photoresist deposited which is patterned with the spaces as lines, and then developed and trimmed. A polymer is deposited over the space photoresist structures and, when hardened, is subject to planarizing to expose the photoresist. The photoresist is removed leaving a reverse image polymer which is then used as a mask to anisotropically etch the spaces to form the closely spaced devices.

Reverse lithographic process for semiconductor spaces

In one embodiment, the present invention relates to a method of treating a resist layer involving the steps of providing the resist layer having a first thickness, the resist layer comprising a polymer having a labile group; contacting a coating containing at least one cleaving compound with the resist layer to form a deprotected resist layer at an interface between the resist layer and the coating; and removing the coating and the deprotected resist layer leaving a resist having a second thickness, wherein the second thickness is smaller than the first thickness.

Chemical resist thickness reduction process

A reverse lithographic process is provided for more densely packing semiconductors onto a semiconductor wafer. A semiconductor wafer having a dielectric covered semiconductor device has a photoresist deposited which is patterned with vias in closely packed rows and columns. The resist is developed and trimmed to form via photoresist structures. A non-photosensitive polymer is deposited over the via photoresist structures and, when hardened, is subject to planarizing to expose the via photoresist structures. The via photoresist structures are removed and leave a reverse image patterned polymer. The photoresist is removed leaving the reverse image patterned polymer, which is then used to etch the dielectric to form vias to the semiconductor device.

Reverse lithographic process for semiconductor vias

A resist removal method provides for analyzing a patterned resist and determining if rework needs to be performed due to the pattern being incorrect. If the pattern is incorrect, the an entire upper surface of the patterned resist is exposed to mild UV light. The exposed patterned resist is then subjected to a developer, such as an alkaline bath, such that the exposed patterned resist is dissolved away from the substrate, and such that a new layer of resist can be applied and then patterned.

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San Jose, CA, United States of America

Ursula Q Quinto