Qualcomm Incorporated

Saras Micro Devices, Inc.

Urmi Ray

Shiqun Gu

Ratibor Radojcic

Dexter Tamio Chun

Hong Bok We

Jungwon Suh

Ravindra Vaman Shenoy

Eugene Robert Worley

Vidhya Ramachandran

Jon Lasiter

Ryan David Lane

Kwan-Yu Lai

Bartlet H DeProspo

Rajesh Gopalaswamy

Kevin Mark Johnson

Thomas J Beck

Venkatesh Sundaram

Markondeyaraj Pulugurtha

Carlos Riera

Jen-Chwen Lin

Kyle Dasch

Bart Deprospo

Mary Pickens

Dewei Zhu

Xue Bai

Multi-terminal capacitor devices and methods of making multi-terminal capacitor devices are described herein. The multi-terminal capacitor devices may include a plurality of individual capacitors arranged in a single device layer, such as high surface area capacitors. A individual capacitor may include an aluminum foil-based electrode, an aluminum oxide dielectric layer conformal with the aluminum foil-based electrode, and a conductive material electrode, such as a conducting polymer or a conductive ceramic, in conformal contact with the dielectric layer.

Planar high-density aluminum capacitors for stacking and embedding

A package substrate for a semiconductor device includes a first substrate core and an inductor embedded in the first substrate core, the inductor including a magnetic core embedded in the first substrate core and a conductive winding surrounding the magnetic core, the conductive winding including one or more first segments defined by metal patterning on the first substrate core and one or more second segments defined by one or more conductive vias extending through the first substrate core. The package substrate may further include a capacitor embedded in the first substrate core and/or in a second substrate core vertically stacked with the first substrate core.

Embedded inductors and integrated voltage regulators for packaged semiconductor devices

An intergrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

Integrated circuit (IC) package comprising electrostatic discharge (ESD) protection

Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer.

Integrated device comprising flexible connector between integrated circuit (IC) packages

Some features pertain to an integrated device that includes a dielectric layer configured as a base for the integrated device, several redistribution metal layers in the dielectric layer, a first wafer level die coupled to a first surface of the dielectric layer, and a second wafer level die coupled to the first wafer level die. The dielectric layer includes several dielectric layers. In some implementations, the first wafer level die is coupled to the redistribution metal layers through a first set of interconnects. In some implementations, the first wafer level die includes several through substrate vias (TSVs). In some implementations, the second wafer level die is coupled to the redistribution metal layers through a first set of interconnects, the TSVs, a second set of interconnects, and a set of solder balls. In some implementations, the integrated device includes an encapsulation layer that encapsulates the first and second wafer level dies.

Integrated device comprising stacked dies on redistribution layers

An integrated interposer between a first component and a second component includes a substrate. The substrate may have thermal and/or mechanical properties with values lying between the thermal and/or mechanical properties of the first component and the second component. Active devices are disposed on a first surface of the substrate. A contact layer is coupled to the active devices and configured to couple at least the first component and a third component to the integrated interposer. At least one through via(s) is coupled to the contact layer and extends through the substrate to a second surface of the substrate. An interconnect layer is disposed on the second surface of the substrate and coupled to the at least one through via(s). The interconnect layer is configured to couple the second component to the integrated interposer.

Integrated interposer with embedded active devices

Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, a first metal redistribution layer coupled to one of the metal layers, and a second metal redistribution layer coupled to the first metal redistribution layer. The first and second metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the integrated device also includes a third metal redistribution layer. The third metal redistribution layer is coupled to the first and second metal redistribution layers. The third metal redistribution layer is a via. In some implementations, the first, second, and third metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the first, second, and third redistribution layers form a set of windings for the toroid inductor.

Toroid inductor in redistribution layers (RDL) of an integrated device

An integrated circuit package is disclosed that includes a first-pitch die and a second-pitch die. The second-pitch die interconnects to the second-pitch substrate through second-pitch substrates. The first-pitch die interconnects through first-pitch interconnects to an interposer adapter. The pitch of the first-pitch interconnects is too fine for the second-pitch substrate. But the interposer adapter interconnects through second-pitch interconnects to the second-pitch substrate and includes through substrate vias so that I/O signaling between the first-pitch die and the second-pitch die can be conducted through the second-pitch substrate and through the through substrate vias in the interposer adapter.

System-in-package with interposer pitch adapter

A semiconductor die has through silicon vias arranged to reduce warpage. The through silicon vias adjust the coefficient of thermal expansion of the semiconductor die, permit substrate deformation, and also relieve residual stress. The through silicon vias may be located in the edges and/or corners of the semiconductor die. The through silicon vias are stress relief vias that can be supplemented with round corner vias to reducing warpage of the semiconductor die.

Apparatus and method for controlling semiconductor die warpage

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San Diego, CA, United States of America

Urmi Ray