Huawei Technologies Co., Limited

Uri Weiser

Tal Horowitz

Zuguang Wu

Huibin Luo

Yoni Choukroun

Jintang Wang

A multi-thread systolic array includes a plurality of processing elements, each including a processor. Each of the processing elements is configured to: receive a plurality of first inputs from a respective first input source; receive a plurality of second inputs from a respective second input source; the plurality of first inputs and the plurality of second inputs being arranged as a plurality of pairs corresponding to a plurality of threads; schedule, for each operation cycle of the processor, a certain thread of the plurality of threads; and execute a computation operation for the certain thread.

Systems and methods for performing multiplication of one or more matrices using multi-thread systolic arrays

A data processing apparatus is provided comprising a front-end interface electronically coupled to a main processor. The front-end interface is configured to receive data stored in a repository, in particular an external storage and/or a network, determine whether the data is a single-access data or a multiple-access data by analyzing an access parameter designating the data, route the multiple-access data for processing by the main processor, and route the single-access data for pre-processing by the front-end interface and routing results of the pre-processing to the main processor.

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Munich, Germany

Uri Weiser