Motorola Solutions, Inc.

Uri Vallach

Mark Rozental

Ovadia Grossman

Moshe Ben-Ayun

Richard S Young

Ricardo Franco

Moshe Ben Ayun

Claudine Tordjman

Method and apparatus for determining a clock frequency for an electronic processor are provided. One embodiment provides a clock generator for determining a clock frequency for an electronic processor and providing a clock signal to the electronic processor. The clock generator includes a crystal oscillator producing a reference signal and a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal. The clock generator also includes a tuning logic controller electrically coupled to the phase locked loop. The tuning logic controller is configured to program the phase locked loop to a first frequency and determine an integrated circuit process corner of the electronic processor. The tuning logic controller is also configured to determine a second frequency based on the integrated circuit process corner and program the phase locked loop to the second frequency.

Method and apparatus for determining a clock frequency for an electronic processor

Receivers () and methods of adaptively adjusting the receivers based on a received interferer are described. The peak-to-average ratio of a received signal is used to determine the type of interferer. The ratio and interferer type, in addition to the type of on-channel signal, are used to select parameters to adjust the decay time of a peak detector (), and the threshold and hysteresis of a comparator (). The peak detector () and comparator () are used to generate an off-channel flag that indicates the presence of a relatively strong interferer to other modules in the receiver (). If valid data is not present a default set of parameters is provided. The ratio is determined by dividing the maximum peak over the average or a range of ratios is determined by comparing a scaled value of the average to different scaled values of the peak.

Adaptive off-channel detector for receivers

A linear RF transmitter () includes a forward path including a baseband signal combiner () and an RF (radio frequency) power amplifier (), and a linearizing control loop from an output () of the RF power amplifier to an input of the combiner (). A feedback control path () of the loop delivers a baseband error control signal to the combiner. The transmitter further includes a test signal generator () to apply to the combiner in a closed loop level training mode a test signal comprising a voltage Vwhich increases with time in a non-linear manner approaching an asymptotic limit such that in response an output signal produced by the combiner is a voltage Vwhich is substantially constant over a period of time.

RF transmitter and method of operation

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Petach-Tikva, Israel

Uri Vallach